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731c4759dc
* Add Rocket mapper * Bootrom: Adjust Logo write to VRAM Sachen verifies part of the logo in VRAM * Add Sachen mapper
130 lines
3.7 KiB
Verilog
130 lines
3.7 KiB
Verilog
module mbc6 (
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input enable,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [63:0] savestate_data,
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inout [63:0] savestate_back_b,
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input has_ram,
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input [1:0] ram_mask,
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input [5:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire ram_enabled;
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wire has_battery;
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wire [63:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 64'hZ;
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// --------------------- CPU register interface ------------------
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reg [6:0] rom_bank_reg_a;
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reg [6:0] rom_bank_reg_b;
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reg [2:0] ram_bank_reg_a;
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reg [2:0] ram_bank_reg_b;
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reg ram_enable;
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assign savestate_back[ 6: 0] = rom_bank_reg_a;
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assign savestate_back[13: 7] = rom_bank_reg_b;
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assign savestate_back[16:14] = ram_bank_reg_a;
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assign savestate_back[19:17] = ram_bank_reg_b;
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assign savestate_back[ 20] = ram_enable;
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assign savestate_back[63:21] = 0;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg_a <= savestate_data[ 6: 0]; // 7'd0;
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rom_bank_reg_b <= savestate_data[13: 7]; // 7'd0;
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ram_bank_reg_a <= savestate_data[16:14]; // 3'd0;
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ram_bank_reg_b <= savestate_data[19:17]; // 3'd0;
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ram_enable <= savestate_data[ 20]; // 1'b0;
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end else if(~enable) begin
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rom_bank_reg_a <= 7'd0;
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rom_bank_reg_b <= 7'd0;
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ram_bank_reg_a <= 3'd0;
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ram_bank_reg_b <= 3'd0;
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ram_enable <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr) begin
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if (~cart_a15 && !cart_addr[14:13]) begin // $0000-1FFF
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case(cart_addr[12:10])
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3'd0: ram_enable <= (cart_di[3:0] == 4'hA); //RAM enable/disable
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3'd1: ram_bank_reg_a <= cart_di[2:0]; // 4KB RAM bank A ($A000-AFFF)
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3'd2: ram_bank_reg_b <= cart_di[2:0]; // 4KB RAM bank B ($B000-BFFF)
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3'd3: ; // Flash enable
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3'd4: ; // Flash write enable
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default: ;
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endcase
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end
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if (~cart_a15 && cart_addr[14:13] == 2'b01) begin // $2000-3FFF
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case(cart_addr[12:11])
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2'd0: rom_bank_reg_a <= cart_di[6:0]; // 8KB ROM bank A ($4000-5FFF)
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2'd1: ; //rom_flash_sel_a <= (cart_di[3:0] == 4'h8); // ROM/Flash A select
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2'd2: rom_bank_reg_b <= cart_di[6:0]; // 8KB ROM bank B ($6000-7FFF)
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2'd3: ; //rom_flash_sel_b <= (cart_di[3:0] == 4'h8); // ROM/Flash B select
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endcase
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end
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end
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end
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end
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reg [6:0] rom_bank;
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always @* begin
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if (~cart_addr[14]) begin // $0000-3FFF
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rom_bank = { 6'd0, cart_addr[13] };
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end else if (~cart_addr[13]) begin // $4000-5FFF
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rom_bank = rom_bank_reg_a;
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end else begin // $6000-7FFF
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rom_bank = rom_bank_reg_b;
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end
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end
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reg [2:0] ram_bank;
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always @* begin
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if (~cart_addr[12]) begin // $A000-AFFF
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ram_bank = ram_bank_reg_a;
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end else begin // $B000-BFFF
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ram_bank = ram_bank_reg_b;
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end
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end
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// mask address lines to enable proper mirroring
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wire [6:0] rom_bank_m = rom_bank & { rom_mask[5:0], 1'b1 }; // 64x16KB Mask
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wire [2:0] ram_bank_m = ram_bank & { ram_mask[1:0], 1'b1 }; // 4x8KB Mask
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assign mbc_addr = { 3'd0, rom_bank_m, cart_addr[12:0] }; // 8KB ROM Bank 0-127
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assign cram_do = ram_enabled ? cram_di : 8'hFF;
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assign cram_addr = { 2'd0, ram_bank_m, cart_addr[11:0] }; // 4KB RAM Bank 0-7
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assign has_battery = has_ram;
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assign ram_enabled = ram_enable & has_ram;
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endmodule |