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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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e140e715d5
* GBA mode * Megaduck * Rumble * Window start fixes (Ant Soldiers, Mealybug tests) * Custom boot roms
98 lines
2.7 KiB
Verilog
98 lines
2.7 KiB
Verilog
module mbc5 (
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input enable,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input has_ram,
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input [3:0] ram_mask,
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input [8:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b,
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output rumbling
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);
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wire [22:0] mbc_addr;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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assign rumbling = mbc_ram_bank_reg[3];
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wire [3:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask;
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// 0x0000-0x3FFF = Bank 0
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wire [8:0] mbc_rom_bank = (~cart_addr[14]) ? 9'd0 : mbc_rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [8:0] mbc5_rom_bank = mbc_rom_bank & rom_mask; //480
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// --------------------- CPU register interface ------------------
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reg [8:0] mbc_rom_bank_reg;
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reg [3:0] mbc_ram_bank_reg;
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reg mbc_ram_enable;
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assign savestate_back[ 8: 0] = mbc_rom_bank_reg;
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assign savestate_back[12: 9] = mbc_ram_bank_reg;
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assign savestate_back[14:13] = 0;
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assign savestate_back[ 15] = mbc_ram_enable;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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mbc_rom_bank_reg <= savestate_data[ 8: 0]; //9'd1;
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mbc_ram_bank_reg <= savestate_data[12: 9]; //4'd0;
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mbc_ram_enable <= savestate_data[ 15]; //1'b0;
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end else if(~enable) begin
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mbc_rom_bank_reg <= 9'd1;
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mbc_ram_bank_reg <= 4'd0;
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mbc_ram_enable <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr & ~cart_a15) begin
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case(cart_addr[14:13])
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2'b00: mbc_ram_enable <= (cart_di == 8'h0A); //RAM enable/disable
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2'b01: if (cart_addr[12])
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mbc_rom_bank_reg[8] <= cart_di[0]; //ROM bank register 3000-3FFF High bit
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else
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mbc_rom_bank_reg[7:0] <= cart_di; // ROM bank register 2000-2FFF Low 8 bits
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2'b10: mbc_ram_bank_reg <= cart_di[3:0]; // RAM bank register
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endcase
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end
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end
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end
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assign mbc_addr = { mbc5_rom_bank, cart_addr[13:0] }; // 16k ROM Bank 0-480 (0h-1E0h)
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assign ram_enabled = mbc_ram_enable & has_ram;
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assign cram_do = ram_enabled ? cram_di : 8'hFF;
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assign cram_addr = { mbc5_ram_bank, cart_addr[12:0] };
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assign has_battery = (cart_mbc_type == 8'h1B || cart_mbc_type == 8'h1E);
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endmodule |