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731c4759dc
* Add Rocket mapper * Bootrom: Adjust Logo write to VRAM Sachen verifies part of the logo in VRAM * Add Sachen mapper
84 lines
2.3 KiB
Verilog
84 lines
2.3 KiB
Verilog
module mbc2 (
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input enable,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input [1:0] ram_mask,
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input [6:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire ram_enabled;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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// 0x0000-0x3FFF = Bank 0
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wire [3:0] mbc_rom_bank = (~cart_addr[14]) ? 4'd0 : mbc_rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [3:0] mbc2_rom_bank = mbc_rom_bank & rom_mask[3:0]; //16
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// --------------------- CPU register interface ------------------
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reg [3:0] mbc_rom_bank_reg;
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reg mbc_ram_enable;
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assign savestate_back[ 3: 0] = mbc_rom_bank_reg;
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assign savestate_back[14: 4] = 0;
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assign savestate_back[ 15] = mbc_ram_enable;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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mbc_rom_bank_reg <= savestate_data[3: 0]; //4'd1;
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mbc_ram_enable <= savestate_data[ 15]; //1'b0;
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end else if(~enable) begin
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mbc_rom_bank_reg <= 4'd1;
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mbc_ram_enable <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr & ~cart_a15 & ~cart_addr[14]) begin
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if (cart_addr[8])
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mbc_rom_bank_reg <= (cart_di[3:0] == 4'd0) ? 4'd1 : cart_di[3:0]; //write to ROM bank register
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else
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mbc_ram_enable <= (cart_di[3:0] == 4'ha); //RAM enable/disable
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end
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end
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end
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assign mbc_addr = { 5'd0, mbc2_rom_bank, cart_addr[13:0] }; // 16k ROM Bank 0-15
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assign cram_do = mbc_ram_enable ? { 4'hF,cram_di[3:0] } : 8'hFF; // 4 bit MBC2 Ram needs top half masked.
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assign cram_addr = { 8'd0, cart_addr[8:0] }; // 512x4bits RAM built in MBC2
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assign has_battery = (cart_mbc_type == 8'h06);
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assign ram_enabled = mbc_ram_enable;
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endmodule |