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731c4759dc
* Add Rocket mapper * Bootrom: Adjust Logo write to VRAM Sachen verifies part of the logo in VRAM * Add Sachen mapper
114 lines
3.4 KiB
Verilog
114 lines
3.4 KiB
Verilog
module mbc1 (
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input enable,
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input mbc1m,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input has_ram,
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input [1:0] ram_mask,
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input [6:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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// https://forums.nesdev.com/viewtopic.php?p=168940#p168940
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// https://gekkio.fi/files/gb-docs/gbctr.pdf
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// MBC1 $6000 Mode register:
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// 0: Bank2 ANDed with CPU A14. Bank2 affects ROM 0x4000-0x7FFF only
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// 1: Passthrough. Bank2 affects ROM 0x0000-0x3FFF, 0x4000-0x7FFF, RAM 0xA000-0xBFFF
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wire [1:0] mbc1_bank2 = mbc_ram_bank_reg[1:0] & {2{cart_addr[14] | mbc1_mode}};
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wire [1:0] mbc1_ram_bank = mbc1_bank2 & ram_mask[1:0];
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// 0x0000-0x3FFF = Bank 0
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wire [4:0] mbc_rom_bank = (~cart_addr[14]) ? 5'd0 : mbc_rom_bank_reg;
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// MBC1: 4x32 16KByte banks, MBC1M: 4x16 16KByte banks
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wire [6:0] mbc1_rom_bank_mode = mbc1m ? { 1'b0, mbc1_bank2, mbc_rom_bank[3:0] }
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: { mbc1_bank2, mbc_rom_bank[4:0] };
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// mask address lines to enable proper mirroring
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wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask[6:0]; //128
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// --------------------- CPU register interface ------------------
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reg mbc_ram_enable;
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reg mbc1_mode;
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reg [4:0] mbc_rom_bank_reg;
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reg [1:0] mbc_ram_bank_reg;
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assign savestate_back[ 4: 0] = mbc_rom_bank_reg;
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assign savestate_back[ 8: 5] = 0;
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assign savestate_back[10: 9] = mbc_ram_bank_reg;
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assign savestate_back[12:11] = 0;
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assign savestate_back[ 13] = mbc1_mode;
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assign savestate_back[ 14] = 0;
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assign savestate_back[ 15] = mbc_ram_enable;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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mbc_rom_bank_reg <= savestate_data[4 : 0]; //5'd1;
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mbc_ram_bank_reg <= savestate_data[10: 9]; //2'd0;
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mbc1_mode <= savestate_data[ 13]; //1'b0;
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mbc_ram_enable <= savestate_data[ 15]; //1'b0;
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end else if(~enable) begin
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mbc_rom_bank_reg <= 5'd1;
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mbc_ram_bank_reg <= 2'd0;
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mbc1_mode <= 1'b0;
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mbc_ram_enable <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr & ~cart_a15) begin
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case(cart_addr[14:13])
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2'b00: mbc_ram_enable <= (cart_di[3:0] == 4'ha); //RAM enable/disable
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2'b01: mbc_rom_bank_reg <= (cart_di[4:0] == 0) ? 5'd1 : cart_di[4:0]; //write to ROM bank register
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2'b10: mbc_ram_bank_reg <= cart_di[1:0]; //write to RAM bank register
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2'b11: mbc1_mode <= cart_di[0]; // MBC1 ROM/RAM Mode Select
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endcase
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end
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end
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end
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assign mbc_addr = { 2'b00, mbc1_rom_bank, cart_addr[13:0] }; // 16k ROM Bank 0-127 or MBC1M Bank 0-63
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assign ram_enabled = mbc_ram_enable & has_ram;
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assign cram_do = ram_enabled ? cram_di : 8'hFF;
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assign cram_addr = { 2'b00, mbc1_ram_bank, cart_addr[12:0] };
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assign has_battery = (cart_mbc_type == 8'h03);
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endmodule |