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4ce2e405a1
Fix freezes in Tokyo Disneyland - Fantasy Tour (Minnie's house) & Daiku no Gen-san - Kachikachi no Tonkachi ga Kachi (Stage 1-4)
112 lines
3.0 KiB
Verilog
112 lines
3.0 KiB
Verilog
module gb_camera (
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input enable,
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input reset,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input [3:0] ram_mask,
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input [8:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_rd,
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input cart_wr,
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input [7:0] cart_di,
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inout cart_oe_b,
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input cram_rd,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire cart_oe;
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wire ram_enabled;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign cart_oe_b = enable ? cart_oe : 1'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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// --------------------- CPU register interface ------------------
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reg [5:0] rom_bank_reg;
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reg [3:0] ram_bank_reg;
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reg ram_write_en;
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reg cam_en;
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assign savestate_back[ 5: 0] = rom_bank_reg;
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assign savestate_back[ 8: 6] = 0;
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assign savestate_back[12: 9] = ram_bank_reg;
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assign savestate_back[ 13] = 0;
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assign savestate_back[ 14] = cam_en;
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assign savestate_back[ 15] = ram_write_en;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg <= savestate_data[ 5: 0]; //6'd1;
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ram_bank_reg <= savestate_data[12: 9]; //4'd0;
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cam_en <= savestate_data[ 14]; //1'b0;
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ram_write_en <= savestate_data[ 15]; //1'b0;
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end else if(~enable) begin
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rom_bank_reg <= 6'd1;
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ram_bank_reg <= 4'd0;
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cam_en <= 1'b0;
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ram_write_en <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr & ~cart_a15) begin
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case(cart_addr[14:13])
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2'b00: ram_write_en <= (cart_di[3:0] == 4'ha); //RAM write enable/disable
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2'b01: rom_bank_reg <= cart_di[5:0]; //write to ROM bank register
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2'b10: begin
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if (cart_di[4]) begin
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cam_en <= 1'b1; //enable CAM registers
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end else begin
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cam_en <= 1'b0; //enable RAM
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ram_bank_reg <= cart_di[3:0]; //write to RAM bank register
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end
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end
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endcase
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end
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end
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end
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wire [3:0] ram_bank = ram_bank_reg & ram_mask[3:0];
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// 0x0000-0x3FFF = Bank 0
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wire [5:0] rom_bank = (~cart_addr[14]) ? 6'd0 : rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [5:0] rom_bank_m = rom_bank & rom_mask[5:0]; //64
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assign mbc_addr = { 3'b000, rom_bank_m, cart_addr[13:0] }; // 16k ROM Bank 0-63
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assign cram_do = cam_en ? 8'h00 : cram_di; // Reading from RAM or CAM is always enabled
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assign cram_addr = { ram_bank, cart_addr[12:0] };
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assign cart_oe = (cart_rd & ~cart_a15) | cram_rd;
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assign has_battery = 1;
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assign ram_enabled = ~cam_en & ram_write_en; // Writing RAM
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endmodule |