From eefc8e1993bfea18193ec23b6312bafdef09a4bb Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sun, 2 Dec 2018 00:20:45 +0800 Subject: [PATCH] Fix some warnings. --- Gameboy.srf | 3 +++ Gameboy.sv | 10 +++++----- gbc_snd.vhd | 5 ++++- t80/T80.vhd | 5 +++-- t80/T80_MCode.vhd | 2 +- video.v | 3 ++- 6 files changed, 18 insertions(+), 10 deletions(-) diff --git a/Gameboy.srf b/Gameboy.srf index 35a7eff..e3b5b1f 100644 --- a/Gameboy.srf +++ b/Gameboy.srf @@ -13,6 +13,8 @@ { "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} @@ -27,3 +29,4 @@ { "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Gameboy.sv b/Gameboy.sv index dd76392..09d7231 100644 --- a/Gameboy.sv +++ b/Gameboy.sv @@ -396,14 +396,14 @@ wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3); wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6); -wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14); +//wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14); wire mbc3 = (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type == 17) || (cart_mbc_type == 18) || (cart_mbc_type == 19); -wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23); +//wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23); wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30); -wire tama5 = (cart_mbc_type == 253); +//wire tama5 = (cart_mbc_type == 253); //wire tama6 = (cart_mbc_type == ???); -wire HuC1 = (cart_mbc_type == 254); -wire HuC3 = (cart_mbc_type == 255); +//wire HuC1 = (cart_mbc_type == 254); +//wire HuC3 = (cart_mbc_type == 255); wire [8:0] mbc_bank = mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram diff --git a/gbc_snd.vhd b/gbc_snd.vhd index 29d0e8c..848b15a 100644 --- a/gbc_snd.vhd +++ b/gbc_snd.vhd @@ -424,7 +424,10 @@ begin end if; end process; - process(s1_addr) + process(s1_addr, sq1_swper, sq1_swdir, sq1_swshift, sq1_duty, sq1_svol, sq1_envsgn, sq1_envper, sq1_lenchk, + noi_playing, wav_playing, sq2_playing, sq1_playing, wav_enable, wav_volsh, wav_ram, + sq2_duty, sq2_svol, sq2_envsgn, sq2_envper, sq2_lenchk, snd_enable, wav_lenchk, noi_svol, noi_envsgn, noi_envper, + noi_freqsh, noi_short, noi_div, noi_lenchk, ch_vol, ch_map) begin case s1_addr is -- Square 1 diff --git a/t80/T80.vhd b/t80/T80.vhd index d3c7197..9407cbb 100644 --- a/t80/T80.vhd +++ b/t80/T80.vhd @@ -856,14 +856,15 @@ begin end if; end process; + TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux))); + process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP) + ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, SP, TmpAddr2) begin RegDIH <= Save_Mux; RegDIL <= Save_Mux; if LDHLSP = '1' and MCycle = "010" and TState = 4 then - TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux))); RegDIH <= TmpAddr2(15 downto 8); RegDIL <= TmpAddr2(7 downto 0); end if; diff --git a/t80/T80_MCode.vhd b/t80/T80_MCode.vhd index f94afb5..8141ed9 100644 --- a/t80/T80_MCode.vhd +++ b/t80/T80_MCode.vhd @@ -186,7 +186,7 @@ architecture rtl of T80_MCode is begin - process (IR, ISet, MCycle, F, NMICycle, IntCycle) + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) variable DDD : std_logic_vector(2 downto 0); variable SSS : std_logic_vector(2 downto 0); variable DPair : std_logic_vector(1 downto 0); diff --git a/video.v b/video.v index 46ce22f..a823ac9 100644 --- a/video.v +++ b/video.v @@ -51,6 +51,7 @@ module video ( localparam STAGE2 = 9'd250; // oam + disp + pause localparam OAM_LEN = 80; +localparam OAM_LEN16 = OAM_LEN/16; wire sprite_pixel_active; wire [1:0] sprite_pixel_data; @@ -58,7 +59,7 @@ wire sprite_pixel_cmap; wire sprite_pixel_prio; wire [7:0] oam_do; -wire [3:0] sprite_index = h_cnt[7:4]-(OAM_LEN/16); // memory io starts at h_cnt == 16 +wire [3:0] sprite_index = h_cnt[7:4] - OAM_LEN16[3:0]; // memory io starts at h_cnt == 16 wire [10:0] sprite_addr; // "data strobe" for the two bytes each sprite line consists of