From b67ee7fdc9e8dfd0e8231b9d223140d4154bb364 Mon Sep 17 00:00:00 2001
From: unknown <bgouveia@gmail.com>
Date: Wed, 24 Oct 2018 01:49:02 +0100
Subject: [PATCH] reset internal counter when reseting div

---
 timer.v | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/timer.v b/timer.v
index 470aba3..cef7041 100644
--- a/timer.v
+++ b/timer.v
@@ -45,9 +45,14 @@ module timer (
 // clk_div[8] = 8khz
 // clk_div[9] = 4khz
 
+wire resetdiv = cpu_sel && cpu_wr && (cpu_addr == 2'b00); //resetdiv also resets internal counter
+
 reg [9:0] clk_div;
-always @(posedge clk)
-	clk_div <= clk_div + 10'd1;
+always @(posedge clk or posedge resetdiv)
+	if(resetdiv)
+	  clk_div <= 10'd6;
+	else
+	  clk_div <= clk_div + 10'd1;
 
 reg [7:0] div;
 reg [7:0] tma;