From f80ff10660f425423e733ef465cff26a4a87af2a Mon Sep 17 00:00:00 2001 From: Bruno Duarte Gouveia Date: Fri, 7 Dec 2018 18:48:46 +0000 Subject: [PATCH 1/4] VIDEO: added 10:9 aspect ratio --- Gameboy.sv | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Gameboy.sv b/Gameboy.sv index be9a63b..5e65786 100644 --- a/Gameboy.sv +++ b/Gameboy.sv @@ -118,8 +118,13 @@ assign LED_USER = ioctl_download; assign LED_DISK = 0; assign LED_POWER = 0; -assign VIDEO_ARX = status[3] ? 8'd16 : 8'd4; -assign VIDEO_ARY = status[3] ? 8'd9 : 8'd3; +assign VIDEO_ARX = status[4:3] == 2'b10 ? 8'd16: + status[4:3] == 2'b01 ? 8'd10: + 8'd4; + +assign VIDEO_ARY = status[4:3] == 2'b10 ? 8'd9: + status[4:3] == 2'b01 ? 8'd9: + 8'd3; assign AUDIO_MIX = status[8:7]; @@ -130,7 +135,7 @@ localparam CONF_STR1 = { "FS,GBCGB,Load ROM;", "OB,System,Gameboy;", //Stub to disambiguate loading hybrid .gbc games in original gb mode "-;", - "O4,Inverted color,No,Yes;", + "OC,Inverted color,No,Yes;", "O1,Palette,Grayscale,Custom;" }; @@ -140,7 +145,7 @@ localparam CONF_STR2 = { "R9,Load Backup RAM;", "RA,Save Backup RAM;", "-;", - "O3,Aspect ratio,4:3,16:9;", + "O34,Aspect ratio,4:3,10:9,16:9;", "O78,Stereo mix,none,25%,50%,100%;", "-;", "O2,Boot,Normal,Fast;", @@ -518,7 +523,7 @@ lcd lcd ( .clk ( clk_cpu ), .tint ( status[1] ), - .inv ( status[4] ), + .inv ( status[12] ), // Palettes .pal1 (palette[127:104]), From 0a97a34b35ac86c364b6111eb9748e7df78d877a Mon Sep 17 00:00:00 2001 From: Bruno Duarte Gouveia Date: Sat, 8 Dec 2018 18:28:21 +0000 Subject: [PATCH 2/4] LCD: decoupled lcd using a buffer instead of shiftregister, fixes sync issues --- lcd.v | 110 +++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 70 insertions(+), 40 deletions(-) diff --git a/lcd.v b/lcd.v index fd0b8fb..5552a59 100644 --- a/lcd.v +++ b/lcd.v @@ -32,34 +32,48 @@ module lcd ( output [7:0] b ); + +reg [14:0] vbuffer_inptr; +reg vbuffer_write; + +reg [14:0] vbuffer_outptr; +reg [14:0] vbuffer_lineptr; + + +//image buffer 160x144x2bits for now , later 15bits for cgb +dpram #(15,2) vbuffer ( + .clock_a (clk), + .address_a (vbuffer_inptr), + .wren_a (clkena), + .data_a (data), + .q_a (), + + .clock_b (pclk), + .address_b (vbuffer_outptr), + .wren_b (1'b0), //only reads + .data_b (), + .q_b (pixel_reg) +); + +always @(posedge clk) begin + if(!on || (mode==2'd01)) begin //lcd disabled of vsync restart pointer + vbuffer_inptr <= 15'h0; + end else begin + + // end of vsync + if(clkena) begin + vbuffer_inptr <= vbuffer_inptr + 15'd1; + end + + end; +end + + // Mode 00: h-blank // Mode 01: v-blank // Mode 10: oam -// Mode 11: oam and vram +// Mode 11: oam and vram -// space for 2*160 pixel -reg [7:0] shift_reg_wptr; -reg p_toggle; -reg [1:0] shift_reg [511:0]; -reg [1:0] last_mode_in; - -// shift register input -always @(posedge clk) begin - last_mode_in <= mode; - - // end of vsync - if(clkena) begin - shift_reg[{p_toggle, shift_reg_wptr}] <= data; - shift_reg_wptr <= shift_reg_wptr + 8'd1; - end - - // reset write pointer at end of hsync phase - if((mode != 2'b00) && (last_mode_in == 2'b00)) begin - shift_reg_wptr <= 8'd0; - p_toggle <= !p_toggle; - end -end - // parameter H = 160; // width of visible area parameter HFP = 16; // unused time before hsync @@ -80,7 +94,6 @@ reg[9:0] v_cnt; // vertical pixel counter reg [1:0] last_mode_h; always@(posedge pclk) begin if(pce) begin - last_mode_h <= mode; if(h_cnt==H+HFP+HS+HBP-1) h_cnt <= 0; else h_cnt <= h_cnt + 1'd1; @@ -89,10 +102,6 @@ always@(posedge pclk) begin if(h_cnt == H+HFP) hs <= 1'b1; if(h_cnt == H+HFP+HS) hs <= 1'b0; - // synchronize to input mode - // end of hblank - if((mode == 2'b10) && (last_mode_h == 2'b00)) - h_cnt <= 0; end end @@ -108,14 +117,6 @@ always@(posedge pclk) begin // generate positive vsync signal if(v_cnt == V+VFP) vs <= 1'b1; if(v_cnt == V+VFP+VS) vs <= 1'b0; - - last_mode_v <= mode; - - // synchronize to input mode - // end of mode 01 (vblank) - // make and offset of - 4 for the 4 line delay of the scandoubler - if((mode != 2'b01) && (last_mode_v == 2'b01)) - v_cnt <= 10'd616 - 10'd4; end end end @@ -131,15 +132,44 @@ always@(posedge pclk) begin // visible area? if((v_cnt < V) && (h_cnt < H)) begin blank <= 1'b0; - pixel_reg <= shift_reg[{!p_toggle, shift_reg_rptr}]; - shift_reg_rptr <= shift_reg_rptr + 8'd1; end else begin blank <= 1'b1; - shift_reg_rptr <= 8'd0; end end end + +reg [7:0] currentpixel; +reg [1:0] linecnt; +always@(posedge pclk) begin + + if(pce) begin + if(h_cnt == H+HFP+HS+HBP-1) begin + + //reset output at vsync + if(v_cnt == V+VFP) begin + vbuffer_outptr <= 15'd0; + vbuffer_lineptr <= 15'd0; + currentpixel <= 8'd0; + linecnt <= 2'd3; + end + end else + // visible area? + if((v_cnt < V) && (h_cnt < H)) begin + vbuffer_outptr <= vbuffer_lineptr + currentpixel; + if (currentpixel + 8'd1 == 160) begin + currentpixel <= 8'd0; + linecnt <= linecnt - 2'd1; + + //increment vbuffer_lineptr after 4 lines + if (!linecnt) + vbuffer_lineptr <= vbuffer_lineptr + 15'd160; + end else + currentpixel <= currentpixel + 8'd1; + end + end +end + wire [1:0] pixel = on? (pixel_reg ^ {inv,inv}) :2'b00; // gameboy "color" palette From ee928828a772fdb667941dde90dbb7d1d88e5e95 Mon Sep 17 00:00:00 2001 From: Bruno Duarte Gouveia Date: Sun, 9 Dec 2018 21:46:42 +0000 Subject: [PATCH 3/4] MBC: added full support for MBC5(8mb ROM and 128kb SRAM) --- Gameboy.sv | 151 ++++++++++++++++++++++++++++------------------------- 1 file changed, 81 insertions(+), 70 deletions(-) diff --git a/Gameboy.sv b/Gameboy.sv index 5e65786..93e79e2 100644 --- a/Gameboy.sv +++ b/Gameboy.sv @@ -237,7 +237,7 @@ wire palette_download = ioctl_download && (filetype == 8'h05 || filetype == 8'h0 wire [1:0] sdram_ds = cart_download ? 2'b11 : {cart_addr[0], ~cart_addr[0]}; wire [15:0] sdram_do; wire [15:0] sdram_di = cart_download ? ioctl_dout : 16'd0; -wire [23:0] sdram_addr = cart_download? ioctl_addr[24:1]: {3'b000, mbc_bank, cart_addr[12:1]}; +wire [23:0] sdram_addr = cart_download? ioctl_addr[24:1]: {2'b00, mbc_bank, cart_addr[12:1]}; wire sdram_oe = ~cart_download & cart_rd & ~cram_rd; wire sdram_we = cart_download & dn_write; @@ -283,79 +283,76 @@ end /////////////////////////////////////////////////// -// TODO: RAM bank // http://fms.komkon.org/GameBoy/Tech/Carts.html // 32MB SDRAM memory map using word addresses // 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D // 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S // ------------------------------------------------- -// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM -// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM +// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM (MBC1-3), 8MB for MBC5 // 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0) -// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1) // --------------------------------------------------------------- // ----------------------------- MBC1 ---------------------------- // --------------------------------------------------------------- -wire [8:0] mbc1_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 +wire [9:0] mbc1_addr = + (cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{2'b00, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 9'd0; -wire [8:0] mbc2_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{1'b0, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15 +wire [9:0] mbc2_addr = + (cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{2'b00, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15 9'd0; -wire [8:0] mbc3_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{mbc3_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 +wire [9:0] mbc3_addr = + (cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{2'b00,mbc3_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 9'd0; -wire [8:0] mbc5_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{mbc5_rom_bank, cart_addr[13]}: // 16k ROM Bank 0-127 for now , TODO: 0-480 after remapping sdram memory +wire [9:0] mbc5_addr = + (cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{mbc5_rom_bank, cart_addr[13]}: // 16k ROM Bank 0-480 (0h-1E0h) 9'd0; // -------------------------- RAM banking ------------------------ // in mode 0 (16/8 mode) the ram is not banked // in mode 1 (4/32 mode) four ram banks are used -wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc_ram_bank_reg:2'b00) & ram_mask; -wire [1:0] mbc3_ram_bank = mbc_ram_bank_reg & ram_mask; -wire [1:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask; +wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc_ram_bank_reg[1:0]:2'b00) & ram_mask[1:0]; +wire [1:0] mbc3_ram_bank = mbc_ram_bank_reg[1:0] & ram_mask[1:0]; +wire [3:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask; // -------------------------- ROM banking ------------------------ // in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines // in mode 1 (4/32 mode) the upper two rom address lines are 2'b00 -wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc_ram_bank_reg, mbc_rom_bank_reg[4:0]}; +wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc_ram_bank_reg[1:0], mbc_rom_bank_reg[4:0]}; // in mode 0 map memory at A000-BFFF // in mode 1 map rtc register at A000-BFFF //wire [6:0] mbc3_ram_bank_addr = { mbc3_mode?2'b00:mbc3_ram_bank_reg, mbc3_rom_bank_reg}; // mask address lines to enable proper mirroring -wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask;//128 -wire [6:0] mbc2_rom_bank = mbc_rom_bank_reg & rom_mask; //16 -wire [6:0] mbc3_rom_bank = mbc_rom_bank_reg & rom_mask; //128 -wire [6:0] mbc5_rom_bank = mbc_rom_bank_reg & rom_mask; //128 for now +wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask[6:0]; //128 +wire [6:0] mbc2_rom_bank = mbc_rom_bank_reg[6:0] & rom_mask[6:0]; //16 +wire [6:0] mbc3_rom_bank = mbc_rom_bank_reg[6:0] & rom_mask[6:0]; //128 +wire [8:0] mbc5_rom_bank = mbc_rom_bank_reg & rom_mask; //480 // --------------------- CPU register interface ------------------ reg mbc_ram_enable; reg mbc1_mode; reg mbc3_mode; -reg [6:0] mbc_rom_bank_reg; // for now reg [8:0] when remapping sdram for 8mb rom (mbc5) -reg [1:0] mbc_ram_bank_reg; // for now reg [2:0] when remapping sdram for 8mb rom (mbc5) +reg [8:0] mbc_rom_bank_reg; +reg [3:0] mbc_ram_bank_reg; //0-15 always @(posedge clk_sys) begin if(reset) begin mbc_rom_bank_reg <= 5'd1; - mbc_ram_bank_reg <= 2'd0; + mbc_ram_bank_reg <= 4'd0; mbc1_mode <= 1'b0; mbc3_mode <= 1'b0; mbc_ram_enable <= 1'b0; @@ -363,10 +360,15 @@ always @(posedge clk_sys) begin //write to ROM bank register if(cart_wr && (cart_addr[15:13] == 3'b001)) begin - if(~mbc5 && cart_di[4:0]==0) + if(~mbc5 && cart_di[6:0]==0) //special case mbc1-3 rombank 0=1 mbc_rom_bank_reg <= 5'd1; - else - mbc_rom_bank_reg <= cart_di[6:0]; + else if (mbc5) begin + if (cart_addr[13:12] == 2'b11) //3000-3FFF High bit + mbc_rom_bank_reg[8] <= cart_di[0]; + else //2000-2FFF low 8 bits + mbc_rom_bank_reg[7:0] <= cart_di[7:0]; + end else + mbc_rom_bank_reg <= {2'b00,cart_di[6:0]}; //mbc1-3 end //write to RAM bank register @@ -376,10 +378,13 @@ always @(posedge clk_sys) begin mbc3_mode <= 1'b1; //enable RTC else begin mbc3_mode <= 1'b0; //enable RAM - mbc_ram_bank_reg <= cart_di[1:0]; + mbc_ram_bank_reg <= {2'b00,cart_di[1:0]}; end end else - mbc_ram_bank_reg <= cart_di[1:0]; + if (mbc5)//can probably be simplified + mbc_ram_bank_reg <= cart_di[3:0]; + else + mbc_ram_bank_reg <= {2'b00,cart_di[1:0]}; end // MBC1 ROM/RAM Mode Select @@ -400,25 +405,26 @@ reg [7:0] cart_rom_size; reg [7:0] cart_ram_size; // RAM size -wire [1:0] ram_mask = // 0 - no ram - (cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank - (cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank - 2'b11; // 3 - 32k, 4 banks - +wire [3:0] ram_mask = // 0 - no ram + (cart_ram_size == 1)?4'b0000: // 1 - 2k, 1 bank + (cart_ram_size == 2)?4'b0000: // 2 - 8k, 1 bank + (cart_ram_size == 3)?4'b0011: // 3 - 32k, 4 banks + 4'b1111; // 4 - 128k 16 banks + // ROM size -wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped - (cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k - (cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k - (cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k - (cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k - (cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M - (cart_rom_size == 6)?7'b1111111: // 6 - 128 banks = 2M -//? (cart_rom_size == 6)?7'b1111111: // 7 - ??? banks = 4M -//? (cart_rom_size == 6)?7'b1111111: // 8 - ??? banks = 8M - (cart_rom_size == 82)?7'b1000111: //$52 - 72 banks = 1.1M - (cart_rom_size == 83)?7'b1001111: //$53 - 80 banks = 1.2M -// (cart_rom_size == 84)?7'b1011111: - 7'b1011111; // $54 - 96 banks = 1.5M +wire [8:0] rom_mask = // 0 - 2 banks, 32k direct mapped + (cart_rom_size == 1)? 9'b000000011: // 1 - 4 banks = 64k + (cart_rom_size == 2)? 9'b000000111: // 2 - 8 banks = 128k + (cart_rom_size == 3)? 9'b000001111: // 3 - 16 banks = 256k + (cart_rom_size == 4)? 9'b000011111: // 4 - 32 banks = 512k + (cart_rom_size == 5)? 9'b000111111: // 5 - 64 banks = 1M + (cart_rom_size == 6)? 9'b001111111: // 6 - 128 banks = 2M + (cart_rom_size == 7)? 9'b011111111: // 7 - 256 banks = 4M + (cart_rom_size == 8)? 9'b111111111: // 8 - 512 banks = 8M + (cart_rom_size == 82)?9'b001111111: //$52 - 72 banks = 1.1M + (cart_rom_size == 83)?9'b001111111: //$53 - 80 banks = 1.2M + (cart_rom_size == 84)?9'b001111111: + 9'b001111111; //$54 - 96 banks = 1.5M wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3); wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6); @@ -431,7 +437,7 @@ wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == //wire HuC1 = (cart_mbc_type == 254); //wire HuC3 = (cart_mbc_type == 255); -wire [8:0] mbc_bank = +wire [9:0] mbc_bank = mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram mbc2?mbc2_addr: // MBC2, 16k bank 0, 16k bank 1-15 + ram mbc3?mbc3_addr: @@ -439,7 +445,7 @@ wire [8:0] mbc_bank = // tama5?tama5_addr: // HuC1?HuC1_addr: // HuC3?HuC3_addr: - {7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address + {8'd0, cart_addr[14:13]}; // no MBC, 32k linear address reg [127:0] palette = 128'h828214517356305A5F1A3B4900000000; @@ -568,7 +574,7 @@ end ///////////////////////// BRAM SAVE/LOAD ///////////////////////////// -wire [14:0] bk_addr = {sd_lba[5:0],sd_buff_addr}; +wire [16:0] bk_addr = {sd_lba[7:0],sd_buff_addr}; wire bk_wr = sd_buff_wr & sd_ack; wire [15:0] bk_data = sd_buff_dout; wire [15:0] bk_q; @@ -590,40 +596,36 @@ wire [7:0] cram_q_l; wire is_cram_addr = (cart_addr[15:13] == 3'b101); wire cram_rd = cart_rd & is_cram_addr; wire cram_wr = cart_wr & is_cram_addr; -wire [14:0] cram_addr = - mbc1 ? - {mbc1_ram_bank, cart_addr[12:0]}: - mbc3 ? - {mbc3_ram_bank, cart_addr[12:0]}: - mbc5 ? - {mbc5_ram_bank, cart_addr[12:0]}: - {2'b00, cart_addr[12:0]}; +wire [16:0] cram_addr = mbc1? {2'b00,mbc1_ram_bank, cart_addr[12:0]}: + mbc3? {2'b00,mbc3_ram_bank, cart_addr[12:0]}: + mbc5? {mbc5_ram_bank, cart_addr[12:0]}: + {4'd0, cart_addr[12:0]}; -// Up to 8kb * 4banks of Cart Ram +// Up to 8kb * 16banks of Cart Ram (128kb) -dpram #(14) cram_l ( +dpram #(16) cram_l ( .clock_a (clk_cpu), - .address_a (cram_addr[14:1]), + .address_a (cram_addr[16:1]), .wren_a (cram_wr & ~cram_addr[0]), .data_a (cart_di), .q_a (cram_q_l), .clock_b (clk_sys), - .address_b (bk_addr[14:1]), + .address_b (bk_addr[16:1]), .wren_b (bk_wr & ~bk_addr[0]), .data_b (bk_data[7:0]), .q_b (bk_q[7:0]) ); -dpram #(14) cram_h ( +dpram #(16) cram_h ( .clock_a (clk_cpu), - .address_a (cram_addr[14:1]), + .address_a (cram_addr[16:1]), .wren_a (cram_wr & cram_addr[0]), .data_a (cart_di), .q_a (cram_q_h), .clock_b (clk_sys), - .address_b (bk_addr[14:1]), + .address_b (bk_addr[16:1]), .wren_b (bk_wr & bk_addr[0]), .data_b (bk_data[15:8]), .q_b (bk_q[15:8]) @@ -647,6 +649,14 @@ wire bk_save = status[10]; reg bk_loading = 0; reg bk_state = 0; +// RAM size +wire [7:0] ram_mask_file = // 0 - no ram + (mbc2)?8'h01: // mbc2 512x4bits + (cart_ram_size == 1)?8'h03: // 1 - 2k, 1 bank sd_lba[1:0] + (cart_ram_size == 2)?8'h0F: // 2 - 8k, 1 bank sd_lba[3:0] + (cart_ram_size == 3)?8'h3F: // 3 - 32k, 4 banks sd_lba[5:0] + 8'hFF; // 4 - 128k 16 banks sd_lba[7:0] 1111 + always @(posedge clk_sys) begin reg old_load = 0, old_save = 0, old_ack; @@ -666,7 +676,8 @@ always @(posedge clk_sys) begin end end else begin if(old_ack & ~sd_ack) begin - if(&sd_lba[5:0]) begin + + if(sd_lba[7:0]>=ram_mask_file) begin bk_loading <= 0; bk_state <= 0; end else begin From cab9b21ba70451af1012eee0874ff2c3023d0c1b Mon Sep 17 00:00:00 2001 From: Bruno Duarte Gouveia Date: Mon, 10 Dec 2018 15:15:18 +0000 Subject: [PATCH 4/4] fixed warnings --- gb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gb.v b/gb.v index 5513f08..c2b2a8b 100644 --- a/gb.v +++ b/gb.v @@ -166,7 +166,7 @@ always @(posedge clk) begin sc_start <= cpu_do[7]; sc_shiftclock <= cpu_do[0]; if (cpu_do[7]) begin //enable transfer - serial_clk_div <= 9'h3FF; + serial_clk_div <= 9'h1FF; serial_counter <= 4'd8; end end else if (sc_start && sc_shiftclock) begin // serial transfer and serial clock enabled @@ -179,7 +179,7 @@ always @(posedge clk) begin if (!serial_counter) begin serial_irq <= 1'b1; //trigger interrupt sc_start <= 1'b0; //reset transfer state - serial_clk_div <= 9'h3FF; + serial_clk_div <= 9'h1FF; serial_counter <= 4'd8; end