From 3ed9bb60e669402c758d4ea3652e7285fe3d1b82 Mon Sep 17 00:00:00 2001
From: Bruno Duarte Gouveia <bgouveia@gmail.com>
Date: Thu, 9 May 2019 22:52:37 +0100
Subject: [PATCH] GENERAL:  wired clk_sys to the gb module, using ce and ce_2x
 to generate the needed clocks internally, general code cleanup

---
 Gameboy.sv | 12 ++++++------
 gb.v       | 22 ++++++++++++++++------
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/Gameboy.sv b/Gameboy.sv
index 729bc46..6279cad 100644
--- a/Gameboy.sv
+++ b/Gameboy.sv
@@ -529,8 +529,11 @@ always @(posedge clk_sys) if(reset) isGBC <= status[15:14] ? status[15] : !filet
 // the gameboy itself
 gb gb (
 	.reset	    ( reset      ),
-	.clk         ( clk_cpu    ),   // the whole gameboy runs on 4mhnz
-	.clk2x       ( clk_cpu2x  ),   // ~8MHz in dualspeed mode (GBC)
+	
+	.clk_sys     ( clk_sys    ),
+	.ce          ( ce_cpu     ),   // the whole gameboy runs on 4mhnz
+	.ce_2x       ( ce_cpu2x   ),   // ~8MHz in dualspeed mode (GBC)
+	
 	.new_game_load  ( cart_download),
 
 	.fast_boot   ( 0          ),
@@ -644,16 +647,13 @@ dpram_dif #(12,8,11,16) boot_rom_gbc (
 
 /////////////////////////  GAME GENIE //////////////////////////////////
 
-reg [34:0] gg_code;
+reg [34:0] gg_code=35'd0;
 
 // Code layout:
 // {clock bit, enable, compare enable, 15'b address, 8'b compare, 8'b replace}
 //  34         33      32              31:16         15:8         7:0
-reg [3:0] old_ioctl_addr;
 always_ff @(posedge clk_sys) begin
 	gg_code[34] <= 1'b0;
-	old_ioctl_addr <= ioctl_addr[3:0];
-	gg_code[34] <= 1'b0;
 
 	if (ioctl_download && type_gg) begin
 		case (ioctl_addr[3:0])
diff --git a/gb.v b/gb.v
index da72b13..be3237e 100644
--- a/gb.v
+++ b/gb.v
@@ -22,8 +22,10 @@
 module gb (
    input reset,
 	input new_game_load,
-   input clk,
-   input clk2x,
+   
+	input clk_sys,
+	input ce,
+	input ce_2x,
 
 	input fast_boot,
 	input [7:0] joystick,
@@ -135,12 +137,22 @@ wire cpu_iorq_n;
 wire cpu_m1_n;
 wire cpu_mreq_n;
 
-wire cpu_clken = isGBC ? !hdma_active:1'b1;  //when hdma is enabled stop CPU (GBC)
+wire clk = clk_sys & ce;
+wire clk2x = clk_sys & ce_2x;
+
+
+wire current_cpu_ce = cpu_speed ? ce_2x:ce;
+wire clk_cpu = clk_sys & current_cpu_ce;
+
+wire cpu_clken = isGBC && hdma_active ? 1'b0 :current_cpu_ce;  //when hdma is enabled stop CPU (GBC)
+
+
 wire cpu_stop;
+
 	
 GBse cpu (
 	.RESET_n    ( !reset        ),
-	.CLK_n      ( clk_cpu       ),
+	.CLK_n      ( clk_sys       ),
 	.CLKEN      ( cpu_clken     ),
 	.WAIT_n     ( 1'b1          ),
 	.INT_n      ( irq_n         ),
@@ -183,8 +195,6 @@ geniecodes codes (
 // --------------------------------------------------------------------
 // --------------------- Speed Toggle KEY1 (GBC)-----------------------
 // --------------------------------------------------------------------
-wire clk_cpu = cpu_speed?clk2x:clk;
-//wire clk_cpu = clk;
 reg cpu_speed; // - 0 Normal mode (4MHz) - 1 Double Speed Mode (8MHz)
 reg prepare_switch; // set to 1 to toggle speed
 assign speed = cpu_speed;