From 30e4aff6873c3e37a2d4b4b7e32dc0a063382ae6 Mon Sep 17 00:00:00 2001 From: Takiiiiiiii <43725718+Takiiiiiiii@users.noreply.github.com> Date: Sat, 6 Dec 2025 00:19:56 +0800 Subject: [PATCH] Update sys (#276) --- sys/ascal.vhd | 183 ++++++++++++++++++++++++++++++++++-------------- sys/sys.tcl | 4 +- sys/sys_top.sdc | 2 +- sys/sys_top.v | 51 ++++++++++---- 4 files changed, 172 insertions(+), 68 deletions(-) diff --git a/sys/ascal.vhd b/sys/ascal.vhd index 5607e64..a735e6b 100644 --- a/sys/ascal.vhd +++ b/sys/ascal.vhd @@ -103,7 +103,7 @@ USE ieee.numeric_std.ALL; -- DOWNSCALE : True=Support downscaling False=Downscaling disabled -- BYTESWAP : Little/Big endian byte swap -- FRAC : Fractional bits, subpixel resolution --- OHRES : Max. output horizontal resolution. Must be a power of two. +-- OHRES : Max. output horizontal resolution. 1024, 2048, 2304, 2560, 4096 -- (Used for sizing line buffers) -- IHRES : Max. input horizontal resolution. Must be a power of two. -- (Used for sizing line buffers) @@ -125,7 +125,7 @@ ENTITY ascal IS ADAPTIVE : boolean := true; DOWNSCALE_NN : boolean := false; FRAC : natural RANGE 4 TO 8 :=4; - OHRES : natural RANGE 1 TO 4096 :=2048; + OHRES : natural RANGE 1 TO 4096 :=2304; IHRES : natural RANGE 1 TO 2048 :=2048; N_DW : natural RANGE 64 TO 128 := 128; N_AW : natural RANGE 8 TO 32 := 32; @@ -258,6 +258,9 @@ ENTITY ascal IS BEGIN ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure; + + ASSERT OHRES = 1024 OR OHRES = 2048 OR OHRES = 2304 OR + OHRES = 2560 OR OHRES = 4096 REPORT "OHRES" SEVERITY failure; END ENTITY ascal; @@ -289,10 +292,39 @@ ARCHITECTURE rtl OF ascal IS END IF; END FUNCTION to_std_logic; + ---------------------------------------------------------- + FUNCTION ohres_h(CONSTANT r : natural) RETURN natural IS + BEGIN + CASE r IS + WHEN 1024 => RETURN 1024; + WHEN 2048 => RETURN 2048; + WHEN OTHERS => RETURN 4096; + END CASE; + END FUNCTION; + FUNCTION ohres_l(CONSTANT r : natural) RETURN natural IS + BEGIN + CASE r IS + WHEN 1024 => RETURN 1024; + WHEN 2048 | 2304 | 2560 => RETURN 2048; + WHEN OTHERS => RETURN 4096; + END CASE; + END FUNCTION; + FUNCTION ohres_m(CONSTANT r : natural) RETURN natural IS + BEGIN + CASE r IS + WHEN 1024 | 2048 | 2304 => RETURN 256; + WHEN OTHERS => RETURN 512; + END CASE; + END FUNCTION; + + CONSTANT OHRESH : natural := ohres_h(OHRES); + CONSTANT OHRESL : natural := ohres_l(OHRES); + CONSTANT OHRESM : natural := ohres_m(OHRES); + ---------------------------------------------------------- CONSTANT NB_BURST : natural :=ilog2(N_BURST); - CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits - CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length + CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits + CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length ---------------------------------------------------------- TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0); @@ -366,7 +398,7 @@ ARCHITECTURE rtl OF ascal IS SIGNAL i_hacc,i_vacc : uint13; SIGNAL i_hdown,i_vdown : std_logic; SIGNAL i_divcpt : natural RANGE 0 TO 36; - SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1; + SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRESH-1; SIGNAL i_lwr,i_bil : std_logic; SIGNAL i_ldw,i_ldrm : type_pix; SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix; @@ -434,7 +466,7 @@ ARCHITECTURE rtl OF ascal IS SIGNAL o_vrr,o_isync,o_isync2 : std_logic; SIGNAL o_vrr_sync,o_vrr_sync2 : boolean; SIGNAL o_vrr_min,o_vrr_min2 : boolean; - SIGNAL o_vrr_max,o_vrr_max2 : boolean; + SIGNAL o_vrr_max,o_vrr_max2 : boolean; SIGNAL o_vcpt_sync,o_vcpt_sync2, o_vrrmax : uint12; SIGNAL o_sync, o_sync_max : boolean; SIGNAL o_vmin,o_vmax,o_vdisp : uint12; @@ -462,13 +494,21 @@ ARCHITECTURE rtl OF ascal IS SIGNAL o_reset_na : std_logic; SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1); ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check"; - SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1); + SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRESL-1); + SIGNAL o_linf0,o_linf1,o_linf2,o_linf3 : arr_pix(0 TO OHRESM-1); + ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check"; ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check"; ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check"; ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check"; - SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRES-1; - SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix; + ATTRIBUTE ramstyle OF o_linf0 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_linf1 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_linf2 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_linf3 : SIGNAL IS "no_rw_check"; + SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRESH-1; + SIGNAL o_ldr0,o_ldr1,o_ldr2,o_ldr3,o_ldw : type_pix; + SIGNAL o_ler0,o_ler1,o_ler2,o_ler3 : type_pix; + SIGNAL o_lex0,o_lex1,o_lex2,o_lex3 : std_logic; SIGNAL o_wr : unsigned(3 DOWNTO 0); SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3,o_vcpt2 : uint12; SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12; @@ -478,7 +518,7 @@ ARCHITECTURE rtl OF ascal IS SIGNAL o_hfrac : arr_frac(0 TO 9); ATTRIBUTE ramstyle OF o_hfrac : SIGNAL IS "logic"; -- avoid blockram shift register - SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1; + SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRESH-1; SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 11); SIGNAL o_hsp,o_vss : std_logic; SIGNAL o_vcarrym,o_prim : boolean; @@ -496,8 +536,9 @@ ARCHITECTURE rtl OF ascal IS TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15; SIGNAL o_off : arr_uint4(0 TO 2); SIGNAL o_bibu : std_logic :='0'; - SIGNAL o_dcptv : arr_uint12(1 TO 14); - SIGNAL o_dcpt : uint12; + SIGNAL o_dcptv : arr_uint12(13 TO 14); + SIGNAL o_dcpt_clr, o_dcpt_inc : std_logic; + SIGNAL o_dcptv_clr, o_dcptv_inc : std_logic_vector(1 TO 12); SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix; SIGNAL o_hpixq : arr_pixq(2 TO 8); ATTRIBUTE ramstyle OF o_hpixq : SIGNAL IS "logic"; -- avoid blockram shift register @@ -505,7 +546,6 @@ ARCHITECTURE rtl OF ascal IS SIGNAL o_vpix_outer : arr_pix(0 TO 2); SIGNAL o_vpix_inner : arr_pix(0 TO 6); - SIGNAL o_vpe : std_logic; SIGNAL o_div : arr_div(0 TO 2); --uint12; SIGNAL o_dir : arr_frac(0 TO 2); @@ -535,11 +575,11 @@ ARCHITECTURE rtl OF ascal IS END CASE; END FUNCTION; - FUNCTION shift_ipack( i_dw : unsigned(N_DW-1 DOWNTO 0); - acpt : natural RANGE 0 TO 15; - shift : unsigned(0 TO 119); - pix : type_pix; - format : unsigned(1 DOWNTO 0)) RETURN unsigned IS + FUNCTION shift_ipack(i_dw : unsigned(N_DW-1 DOWNTO 0); + acpt : natural RANGE 0 TO 15; + shift : unsigned(0 TO 119); + pix : type_pix; + format : unsigned(1 DOWNTO 0)) RETURN unsigned IS VARIABLE dw : unsigned(N_DW-1 DOWNTO 0); BEGIN dw:=i_dw; @@ -1463,12 +1503,12 @@ BEGIN -- Push pixels to downscaling line buffer i_lwr<=i_hnp4 AND i_ven5 AND i_pce; IF i_lwr='1' THEN - i_lwad<=(i_lwad+1) MOD OHRES; + i_lwad<=(i_lwad+1) MOD OHRESH; END IF; i_ldw<=i_hpix; IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN - i_lrad<=(i_lrad+1) MOD OHRES; + i_lrad<=(i_lrad+1) MOD OHRESH; END IF; ------------------------------------------------------ @@ -1827,7 +1867,7 @@ BEGIN VARIABLE shift_v : unsigned(0 TO N_DW+15); VARIABLE hpix_v : type_pix; VARIABLE hcarry_v,vcarry_v : boolean; - VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1; + VARIABLE dif_v : natural RANGE 0 TO 8*OHRESH-1; VARIABLE off_v : natural RANGE 0 TO 15; BEGIN IF o_reset_na='0' THEN @@ -2142,6 +2182,9 @@ BEGIN ------------------------------------------------------ -- Copy from buffered memory to pixel lines o_sh<='0'; + o_dcpt_clr <= '0'; + o_dcpt_inc <= '0'; + CASE o_copy IS WHEN sWAIT => o_copyv(0)<='0'; @@ -2160,7 +2203,7 @@ BEGIN o_hacc <=o_hacc_ini; o_hacc_next<=o_hacc_ini + 2*o_ihsize; o_hacpt <=x"000"; - o_dcpt<=0; + o_dcpt_clr <= '1'; o_dshi<=2; o_acpt<=0; o_first<='1'; @@ -2188,17 +2231,17 @@ BEGIN WHEN sCOPY => -- dshi : Force shift first two or three pixels of each line IF o_dshi=0 THEN - dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES); - IF dif_v>=4*OHRES THEN + dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRESH)) MOD (8*OHRESH); + IF dif_v>=4*OHRESH THEN o_hacc<=o_hacc_next; o_hacc_next<=o_hacc_next + 2*o_ihsize; hcarry_v:=false; ELSE o_hacc<=dif_v; - o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES); + o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRESH)) MOD (4*OHRESH); hcarry_v:=true; END IF; - o_dcpt<=(o_dcpt+1) MOD 4096; + o_dcpt_inc <= '1'; ELSE o_dshi<=o_dshi-1; hcarry_v:=false; @@ -2568,13 +2611,19 @@ BEGIN o_hfrac(2 TO 9) <= o_hfrac(1 TO 8); o_copyv(1 TO 14)<=o_copyv(0 TO 13); + o_dcptv_clr(1 TO 12)<=o_dcpt_clr & o_dcptv_clr(1 TO 11); + o_dcptv_inc(1 TO 12)<=o_dcpt_inc & o_dcptv_inc(1 TO 11); - o_dcptv(1)<=o_dcpt; - IF o_dcptv(1)>=o_hsize THEN - o_copyv(2)<='0'; + IF o_dcptv_clr(12)='1' THEN + o_dcptv(13) <= 0; + ELSIF o_dcptv_inc(12)='1' THEN + o_dcptv(13) <= (o_dcptv(13) + 1) MOD OHRESH; + END IF; + o_dcptv(14)<=o_dcptv(13); + + IF o_dcptv(13)>=o_hsize THEN + o_copyv(14)<='0'; END IF; - o_dcptv(2)<=o_dcptv(1) MOD OHRES; - o_dcptv(3 TO 14)<=o_dcptv(2 TO 13); -- C2 o_hpixq(2)<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0); @@ -2667,17 +2716,39 @@ BEGIN OLBUF:PROCESS(o_clk) IS BEGIN IF rising_edge(o_clk) THEN + ----------------------------------------------- -- WRITES - IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF; - IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF; - IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF; - IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF; + IF o_wr(0)='1' AND o_wadl < OHRESL THEN o_line0(o_wadl MOD OHRESL)<=o_ldw; END IF; + IF o_wr(1)='1' AND o_wadl < OHRESL THEN o_line1(o_wadl MOD OHRESL)<=o_ldw; END IF; + IF o_wr(2)='1' AND o_wadl < OHRESL THEN o_line2(o_wadl MOD OHRESL)<=o_ldw; END IF; + IF o_wr(3)='1' AND o_wadl < OHRESL THEN o_line3(o_wadl MOD OHRESL)<=o_ldw; END IF; + IF OHRES = 2304 OR OHRES = 2560 THEN + IF o_wr(0)='1' AND o_wadl >= OHRESL THEN o_linf0(o_wadl MOD OHRESM)<=o_ldw; END IF; + IF o_wr(1)='1' AND o_wadl >= OHRESL THEN o_linf1(o_wadl MOD OHRESM)<=o_ldw; END IF; + IF o_wr(2)='1' AND o_wadl >= OHRESL THEN o_linf2(o_wadl MOD OHRESM)<=o_ldw; END IF; + IF o_wr(3)='1' AND o_wadl >= OHRESL THEN o_linf3(o_wadl MOD OHRESM)<=o_ldw; END IF; + END IF; + ----------------------------------------------- -- READS - o_ldr0<=o_line0(o_radl0); - o_ldr1<=o_line1(o_radl1); - o_ldr2<=o_line2(o_radl2); - o_ldr3<=o_line3(o_radl3); + o_ldr0<=o_line0(o_radl0 MOD OHRESL); + o_ldr1<=o_line1(o_radl1 MOD OHRESL); + o_ldr2<=o_line2(o_radl2 MOD OHRESL); + o_ldr3<=o_line3(o_radl3 MOD OHRESL); + + IF OHRES = 2304 OR OHRES = 2560 THEN + o_ler0<=o_linf0(o_radl0 MOD OHRESM); + o_ler1<=o_linf1(o_radl1 MOD OHRESM); + o_ler2<=o_linf2(o_radl2 MOD OHRESM); + o_ler3<=o_linf3(o_radl3 MOD OHRESM); + END IF; + + o_lex0 <= to_std_logic(o_radl0 >= OHRESL); + o_lex1 <= to_std_logic(o_radl1 >= OHRESL); + o_lex2 <= to_std_logic(o_radl2 >= OHRESL); + o_lex3 <= to_std_logic(o_radl3 >= OHRESL); + ----------------------------------------------- + END IF; END PROCESS OLBUF; @@ -2735,17 +2806,17 @@ BEGIN o_pev(2)<='0'; o_end(2)<='0'; END IF; - END IF; - + END IF; + o_vcpt_sync2<=o_vcpt_sync; o_vrr_min<=(o_vcpt_sync2 pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3); - WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0); - WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1); - WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2); + WHEN "10" => pixq_v:=(o_l0_v,o_l1_v,o_l2_v,o_l3_v); + WHEN "11" => pixq_v:=(o_l1_v,o_l2_v,o_l3_v,o_l0_v); + WHEN "00" => pixq_v:=(o_l2_v,o_l3_v,o_l0_v,o_l1_v); + WHEN OTHERS => pixq_v:=(o_l3_v,o_l0_v,o_l1_v,o_l2_v); END CASE; IF fracnn_v = '0' THEN diff --git a/sys/sys.tcl b/sys/sys.tcl index 93b6247..9f3de3e 100644 --- a/sys/sys.tcl +++ b/sys/sys.tcl @@ -65,8 +65,8 @@ set_location_assignment PIN_AD17 -to SDRAM_A[11] set_location_assignment PIN_D12 -to SDRAM_A[12] set_location_assignment PIN_Y17 -to SDRAM_BA[0] set_location_assignment PIN_AB25 -to SDRAM_BA[1] -set_location_assignment PIN_E8 -to SDRAM_DQ[0] -set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_V12 -to SDRAM_DQ[0] +set_location_assignment PIN_E8 -to SDRAM_DQ[1] set_location_assignment PIN_D11 -to SDRAM_DQ[2] set_location_assignment PIN_W12 -to SDRAM_DQ[3] set_location_assignment PIN_AH13 -to SDRAM_DQ[4] diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index ac21334..c2b4118 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -74,4 +74,4 @@ set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_v set_false_path -from {ascal|o_hsize* ascal|o_vsize*} set_false_path -from {mcp23009|flg_*} -set_false_path -to {sysmem|fpga_interfaces|clocks_resets*} +set_false_path -to {sysmem|fpga_interfaces|clocks_resets|f2h*} diff --git a/sys/sys_top.v b/sys/sys_top.v index 18f3969..a646213 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -300,8 +300,9 @@ wire audio_96k = cfg[6]; wire csync_en = cfg[3]; wire io_osd_vga = io_ss1 & ~io_ss2; `ifndef MISTER_DUAL_SDRAM - wire ypbpr_en = cfg[5]; - wire sog = cfg[9]; + wire forced_scandoubler = cfg[4]; + wire ypbpr_en = cfg[5]; + wire sog = cfg[9]; `ifdef MISTER_DEBUG_NOHDMI wire vga_scaler = 0; `else @@ -394,6 +395,7 @@ always@(posedge clk_sys) begin `ifndef MISTER_DEBUG_NOHDMI if(io_din[7:0] == 'h40) io_dout_sys <= fb_crc; `endif + if(io_din[7:0] == 'h42) io_dout_sys <= {1'b1, frame_cnt}; end else begin cnt <= cnt + 1'd1; @@ -500,18 +502,22 @@ always@(posedge clk_sys) begin endcase end `endif -`ifndef MISTER_DISABLE_YC if(cmd == 'h41) begin case(cnt[3:0]) - 0: {pal_en,cvbs,yc_en} <= io_din[2:0]; - 1: PhaseInc[15:0] <= io_din; - 2: PhaseInc[31:16] <= io_din; - 3: PhaseInc[39:32] <= io_din[7:0]; - 4: ColorBurst_Range[15:0] <= io_din; - 5: ColorBurst_Range[16] <= io_din[0]; +`ifndef MISTER_DISABLE_YC + 0: {pal_en,cvbs,yc_en} <= io_din[2:0]; + 4: ColorBurst_Range[15:0] <= io_din; + 5: ColorBurst_Range[16] <= io_din[0]; +`endif + // Subcarrier commands (independent of YC module) + 1: PhaseInc[15:0] <= io_din; + 2: PhaseInc[31:16] <= io_din; + 3: PhaseInc[39:32] <= io_din[7:0]; +`ifndef MISTER_DUAL_SDRAM + 6: subcarrier <= io_din[0]; +`endif endcase end -`endif end end @@ -530,6 +536,15 @@ always@(posedge clk_sys) begin if(~vs_d2 & vs_d1) vs_wait <= 0; end +reg [7:0] frame_cnt; +always @(posedge clk_sys) begin + reg vs_r, vs_old; + + vs_r <= vs_fix; + if(vs_r == vs_fix) vs_old <= vs_r; + if(~vs_old & vs_r) frame_cnt <= frame_cnt + 1'd1; +end + cyclonev_hps_interface_peripheral_uart uart ( .ri(0), @@ -1399,7 +1414,6 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); reg yc_en; reg cvbs; reg [16:0] ColorBurst_Range; - reg [39:0] PhaseInc; wire [23:0] yc_o; wire yc_hs, yc_vs, yc_cs, yc_de; @@ -1423,7 +1437,20 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); ); `endif +reg [39:0] PhaseInc; + `ifndef MISTER_DUAL_SDRAM + // Subcarrier generation for external encoders (independent of YC module) + reg subcarrier; + + reg [39:0] sub_accum; + always @(posedge clk_vid) sub_accum <= sub_accum + PhaseInc; + + // 1-bit output for positive/negative of wave, no LUT required. Output 1 if disabled for further logic + reg subcarrier_out; + always @(posedge clk_vid) subcarrier_out <= ~(subcarrier & csync_en & ~ypbpr_en & ~forced_scandoubler & ~vgas_en) | sub_accum[39]; + + wire VGA_DISABLE; wire [23:0] vgas_o; wire vgas_hs, vgas_vs, vgas_cs, vgas_de; @@ -1476,7 +1503,7 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); wire cs1 = vgas_en ? vgas_cs : vga_cs; wire de1 = vgas_en ? vgas_de : vga_de; - assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); + assign VGA_VS = av_dis ? 1'bZ :(((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en) & subcarrier_out); assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];