mirror of
https://github.com/MiSTer-devel/GameAndWatch_MiSTer.git
synced 2026-05-24 03:03:25 +00:00
198 lines
7.8 KiB
Verilog
198 lines
7.8 KiB
Verilog
// megafunction wizard: %FIFO%
|
|
// GENERATION: STANDARD
|
|
// VERSION: WM1.0
|
|
// MODULE: dcfifo_mixed_widths
|
|
|
|
// ============================================================
|
|
// File Name: image_fifo.v
|
|
// Megafunction Name(s):
|
|
// dcfifo_mixed_widths
|
|
//
|
|
// Simulation Library Files(s):
|
|
// altera_mf
|
|
// ============================================================
|
|
// ************************************************************
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
//
|
|
// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
|
|
// ************************************************************
|
|
|
|
|
|
//Copyright (C) 2022 Intel Corporation. All rights reserved.
|
|
//Your use of Intel Corporation's design tools, logic functions
|
|
//and other software and tools, and any partner logic
|
|
//functions, and any output files from any of the foregoing
|
|
//(including device programming or simulation files), and any
|
|
//associated documentation or information are expressly subject
|
|
//to the terms and conditions of the Intel Program License
|
|
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
//the Intel FPGA IP License Agreement, or other applicable license
|
|
//agreement, including, without limitation, that your use is for
|
|
//the sole purpose of programming logic devices manufactured by
|
|
//Intel and sold by Intel or its authorized distributors. Please
|
|
//refer to the applicable agreement for further details, at
|
|
//https://fpgasoftware.intel.com/eula.
|
|
|
|
|
|
// synopsys translate_off
|
|
`timescale 1 ps / 1 ps
|
|
// synopsys translate_on
|
|
module image_fifo (
|
|
aclr,
|
|
data,
|
|
rdclk,
|
|
rdreq,
|
|
wrclk,
|
|
wrreq,
|
|
q,
|
|
rdempty,
|
|
rdusedw,
|
|
wrfull,
|
|
wrusedw);
|
|
|
|
input aclr;
|
|
input [23:0] data;
|
|
input rdclk;
|
|
input rdreq;
|
|
input wrclk;
|
|
input wrreq;
|
|
output [23:0] q;
|
|
output rdempty;
|
|
output [9:0] rdusedw;
|
|
output wrfull;
|
|
output [9:0] wrusedw;
|
|
`ifndef ALTERA_RESERVED_QIS
|
|
// synopsys translate_off
|
|
`endif
|
|
tri0 aclr;
|
|
`ifndef ALTERA_RESERVED_QIS
|
|
// synopsys translate_on
|
|
`endif
|
|
|
|
wire [23:0] sub_wire0;
|
|
wire sub_wire1;
|
|
wire [9:0] sub_wire2;
|
|
wire sub_wire3;
|
|
wire [9:0] sub_wire4;
|
|
wire [23:0] q = sub_wire0[23:0];
|
|
wire rdempty = sub_wire1;
|
|
wire [9:0] rdusedw = sub_wire2[9:0];
|
|
wire wrfull = sub_wire3;
|
|
wire [9:0] wrusedw = sub_wire4[9:0];
|
|
|
|
dcfifo_mixed_widths dcfifo_mixed_widths_component (
|
|
.aclr (aclr),
|
|
.data (data),
|
|
.rdclk (rdclk),
|
|
.rdreq (rdreq),
|
|
.wrclk (wrclk),
|
|
.wrreq (wrreq),
|
|
.q (sub_wire0),
|
|
.rdempty (sub_wire1),
|
|
.rdusedw (sub_wire2),
|
|
.wrfull (sub_wire3),
|
|
.wrusedw (sub_wire4),
|
|
.eccstatus (),
|
|
.rdfull (),
|
|
.wrempty ());
|
|
defparam
|
|
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
|
|
dcfifo_mixed_widths_component.lpm_numwords = 1024,
|
|
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
|
|
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
|
|
dcfifo_mixed_widths_component.lpm_width = 24,
|
|
dcfifo_mixed_widths_component.lpm_widthu = 10,
|
|
dcfifo_mixed_widths_component.lpm_widthu_r = 10,
|
|
dcfifo_mixed_widths_component.lpm_width_r = 24,
|
|
dcfifo_mixed_widths_component.overflow_checking = "ON",
|
|
dcfifo_mixed_widths_component.rdsync_delaypipe = 3,
|
|
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
|
|
dcfifo_mixed_widths_component.underflow_checking = "ON",
|
|
dcfifo_mixed_widths_component.use_eab = "ON",
|
|
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
|
|
dcfifo_mixed_widths_component.wrsync_delaypipe = 3;
|
|
|
|
|
|
endmodule
|
|
|
|
// ============================================================
|
|
// CNX file retrieval info
|
|
// ============================================================
|
|
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
|
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
|
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
|
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
|
|
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
|
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
|
|
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
|
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
|
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
|
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
|
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
|
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
|
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
|
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
|
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
|
// Retrieval info: PRIVATE: Width NUMERIC "24"
|
|
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
|
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
|
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
|
// Retrieval info: PRIVATE: output_width NUMERIC "24"
|
|
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
|
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
|
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
|
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
|
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
|
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
|
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
|
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
|
|
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
|
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
|
|
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
|
|
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
|
|
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "24"
|
|
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
|
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
|
|
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
|
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
|
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
|
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
|
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
|
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
|
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
|
|
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
|
|
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
|
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
|
|
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
|
// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
|
|
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
|
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
|
|
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
|
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
|
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
|
// Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
|
|
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
|
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
|
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
|
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
|
// Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
|
|
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
|
// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
|
|
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
|
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo.v TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo.inc FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo.cmp FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo.bsf FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo_inst.v FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL image_fifo_bb.v TRUE
|
|
// Retrieval info: LIB_FILE: altera_mf
|