14 Commits

Author	SHA1	Message	Date
Adam Gastineau	d3c0e16be0	Rough pass at documenting SM511/512 instructions	2023-07-30 12:17:27 -07:00
Adam Gastineau	173fb9d7e9	fix: Skip all of two byte instructions	2023-06-29 17:22:10 -07:00
Adam Gastineau	712a10b585	Fixed titles	2023-06-26 14:58:58 -07:00
Adam Gastineau	348f0b7929	Proper handling of SM5a memory mirroring	2023-06-19 10:45:51 -07:00
Adam Gastineau	b1d2904cb6	Properly initialize SM5a stack	2023-06-19 10:21:02 -07:00
Adam Gastineau	5824c568d6	Fixed IDIV and EXCI on SM5a	2023-06-17 10:03:35 -07:00
Adam Gastineau	fa718c9e1d	Beginning of decode and handling of SM5a instructions	2023-06-16 21:25:25 -07:00
Adam Gastineau	d017c0607f	Beginning of SM5a difference docs based on MAME	2023-06-14 11:26:31 -07:00
Adam Gastineau	3342bb8c3f	Fixed subsequent LAX instructions	2023-05-09 20:06:49 -07:00
Adam Gastineau	d03a0e6cad	Fixed skip cycle count and ADD11 incorrecting setting carry	2023-05-08 22:17:18 -07:00
Adam Gastineau	b0e9c074a9	Execution comparison to MAME. Matches all instr through awaiting input	2023-05-07 15:40:23 -07:00
Adam Gastineau	e01837bd6d	First complete pass at implementation	2023-05-06 15:54:52 -07:00
Adam Gastineau	ee084439a3	Initial pass at SM510 instructions	2023-05-05 19:09:19 -07:00
Adam Gastineau	e0dece2589	Initialized Gateware project	2023-05-05 12:04:46 -07:00