From e44c1fa9c09bc4763e76ec42e2d901dd123de236 Mon Sep 17 00:00:00 2001 From: Adam Gastineau Date: Sun, 25 Jun 2023 09:41:41 -0700 Subject: [PATCH] Renamed clk nets --- rtl/gameandwatch.sv | 22 +++++++++++----------- rtl/video/rgb_controller.sv | 16 ++++++++-------- rtl/video/video.sv | 14 +++++++------- target/mimic/core_top.sv | 18 +++++++++--------- target/pocket/core_top.v | 28 ++++++++++++++-------------- 5 files changed, 49 insertions(+), 49 deletions(-) diff --git a/rtl/gameandwatch.sv b/rtl/gameandwatch.sv index aed33a2..a69e105 100644 --- a/rtl/gameandwatch.sv +++ b/rtl/gameandwatch.sv @@ -1,8 +1,8 @@ import types::*; module gameandwatch ( - input wire clk_sys_131_072, - input wire clk_vid_32_768, + input wire clk_sys_99_287, + input wire clk_vid_33_095, input wire reset, input wire pll_core_locked, @@ -71,7 +71,7 @@ module gameandwatch ( wire [3:0] cpu_id = sys_config.mpu[3:0]; rom_loader rom_loader ( - .clk(clk_sys_131_072), + .clk(clk_sys_99_287), .ioctl_download(ioctl_download), .ioctl_wr(ioctl_wr), @@ -100,13 +100,13 @@ module gameandwatch ( reg [7:0] rom[4096]; - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin if (clk_en) begin rom_data <= rom[rom_addr]; end end - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin if (wr_8bit && rom_download) begin // ioctl_dout has flipped bytes, flip back by modifying address rom[{addr_8bit[25:1], ~addr_8bit[0]}] <= data_8bit; @@ -128,7 +128,7 @@ module gameandwatch ( wire input_acl; input_config input_config ( - .clk(clk_sys_131_072), + .clk(clk_sys_99_287), .sys_config(sys_config), @@ -169,7 +169,7 @@ module gameandwatch ( wire clk_en = clock_divider == 0; - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin clock_divider <= clock_divider - 1; if (clock_divider == 0) begin @@ -189,7 +189,7 @@ module gameandwatch ( wire divider_1khz; sm510 sm510 ( - .clk(clk_sys_131_072), + .clk(clk_sys_99_287), .clk_en(clk_en), @@ -239,8 +239,8 @@ module gameandwatch ( video #( .CLOCK_RATIO(3) ) video ( - .clk_sys_131_072(clk_sys_131_072), - .clk_vid_32_768 (clk_vid_32_768), + .clk_sys_99_287(clk_sys_99_287), + .clk_vid_33_095(clk_vid_33_095), .reset(reset || ioctl_download), @@ -287,7 +287,7 @@ module gameandwatch ( .CLOCK_SPEED_MHZ(99.28704), .CAS_LATENCY(2) ) sdram ( - .clk (clk_sys_131_072), + .clk (clk_sys_99_287), .reset(~pll_core_locked), // Port 0 diff --git a/rtl/video/rgb_controller.sv b/rtl/video/rgb_controller.sv index d7c4d66..2c65d34 100644 --- a/rtl/video/rgb_controller.sv +++ b/rtl/video/rgb_controller.sv @@ -1,6 +1,6 @@ module rgb_controller ( - input wire clk_sys_131_072, - input wire clk_vid_32_768, + input wire clk_sys_99_287, + input wire clk_vid_33_095, input wire reset, @@ -25,8 +25,8 @@ module rgb_controller ( wire fifo_clear = hblank_int && ~prev_hblank; image_fifo background_image_fifo ( - .wrclk(clk_sys_131_072), - .rdclk(clk_vid_32_768), + .wrclk(clk_sys_99_287), + .rdclk(clk_vid_33_095), .wrreq(buffer_count == 3'h3), .data (background_buffer), @@ -40,8 +40,8 @@ module rgb_controller ( ); image_fifo mask_image_fifo ( - .wrclk(clk_sys_131_072), - .rdclk(clk_vid_32_768), + .wrclk(clk_sys_99_287), + .rdclk(clk_vid_33_095), .wrreq(buffer_count == 3'h3), .data (mask_buffer), @@ -65,7 +65,7 @@ module rgb_controller ( reg [2:0] buffer_count = 0; reg [15:0] sd_read_count = 0; - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin if (reset) begin background_buffer <= 0; mask_buffer <= 0; @@ -128,7 +128,7 @@ module rgb_controller ( // Address of the next line of the image // Address calculates the number of bytes (not words) so we have full precision // Essentually multiply by two, then divide by to for interleaved data, then byte addressing - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin reg [ 9:0] read_y; reg [25:0] read_byte_addr; diff --git a/rtl/video/video.sv b/rtl/video/video.sv index 9df549b..584385f 100644 --- a/rtl/video/video.sv +++ b/rtl/video/video.sv @@ -1,8 +1,8 @@ module video #( parameter CLOCK_RATIO = 3 ) ( - input wire clk_sys_131_072, - input wire clk_vid_32_768, + input wire clk_sys_99_287, + input wire clk_vid_33_095, input wire reset, @@ -58,7 +58,7 @@ module video #( lcd #( .CLOCK_RATIO(CLOCK_RATIO) ) lcd ( - .clk(clk_sys_131_072), + .clk(clk_sys_99_287), .reset(reset), @@ -97,8 +97,8 @@ module video #( assign rgb = reset ? 24'h0 : segment_en ? mask_rgb : background_rgb; rgb_controller rgb_controller ( - .clk_sys_131_072(clk_sys_131_072), - .clk_vid_32_768 (clk_vid_32_768), + .clk_sys_99_287(clk_sys_99_287), + .clk_vid_33_095(clk_vid_33_095), .reset(reset), @@ -124,7 +124,7 @@ module video #( // Sync counts // Delay all signals by 1 cycle so that RGB is caught up - always @(posedge clk_vid_32_768) begin + always @(posedge clk_vid_33_095) begin hsync <= hsync_int; vsync <= vsync_int; hblank <= hblank_int; @@ -134,7 +134,7 @@ module video #( end counts counts ( - .clk(clk_vid_32_768), + .clk(clk_vid_33_095), .x(video_x), .y(video_y), diff --git a/target/mimic/core_top.sv b/target/mimic/core_top.sv index e007bb3..28b81a7 100644 --- a/target/mimic/core_top.sv +++ b/target/mimic/core_top.sv @@ -231,16 +231,16 @@ module core_top ( //////////////////////////////////////////////////////////////////////////////////////// // PLL - wire clk_sys_131_072; - wire clk_vid_32_768; + wire clk_sys_99_287; + wire clk_vid_33_095; wire pll_core_locked; pll pll_core ( .refclk (CLK_50M), .rst (0), - .outclk_0(clk_sys_131_072), - .outclk_1(clk_vid_32_768), + .outclk_0(clk_sys_99_287), + .outclk_1(clk_vid_33_095), .locked (pll_core_locked) ); @@ -269,7 +269,7 @@ module core_top ( // Use 16 bit ioctl .WIDE(1) ) hps_io ( - .clk_sys(clk_sys_131_072), + .clk_sys(clk_sys_99_287), .HPS_BUS(HPS_BUS), .buttons(hps_buttons), @@ -309,7 +309,7 @@ module core_top ( reg prev_ioctl_download = 0; - always @(posedge clk_sys_131_072) begin + always @(posedge clk_sys_99_287) begin prev_ioctl_download <= ioctl_download; // Hold core in reset (to blank video) when there is no ROM @@ -340,8 +340,8 @@ module core_top ( wire sound; gameandwatch gameandwatch ( - .clk_sys_131_072(clk_sys_131_072), - .clk_vid_32_768 (clk_vid_32_768), + .clk_sys_99_287(clk_sys_99_287), + .clk_vid_33_095(clk_vid_33_095), .reset(RESET || ioctl_download || ~has_rom || external_reset || hps_buttons[1]), .pll_core_locked(pll_core_locked), @@ -402,7 +402,7 @@ module core_top ( wire de; wire [23:0] rgb; - assign CLK_VIDEO = clk_vid_32_768; + assign CLK_VIDEO = clk_vid_33_095; assign VGA_DE = de; assign CE_PIXEL = 1; assign VGA_HS = hsync; diff --git a/target/pocket/core_top.v b/target/pocket/core_top.v index f0c3353..699c74e 100644 --- a/target/pocket/core_top.v +++ b/target/pocket/core_top.v @@ -518,7 +518,7 @@ module core_top ( .WRITE_MEM_EN_CYCLE_LENGTH(1) ) data_loader ( .clk_74a(clk_74a), - .clk_memory(clk_sys_131_072), + .clk_memory(clk_sys_99_287), .bridge_wr(bridge_wr), .bridge_endian_little(bridge_endian_little), @@ -551,7 +551,7 @@ module core_top ( ) internal_s ( {ioctl_download, reset_n, pll_core_locked, external_reset, accurate_lcd_timing}, {ioctl_download_s, reset_n_s, pll_core_locked_s, external_reset_s, accurate_lcd_timing_s}, - clk_sys_131_072 + clk_sys_99_287 ); wire [31:0] cont1_key_s; @@ -561,7 +561,7 @@ module core_top ( ) cont1_s ( cont1_key, cont1_key_s, - clk_sys_131_072 + clk_sys_99_287 ); //////////////////////////////////////////////////////////////////////////////////////// @@ -570,8 +570,8 @@ module core_top ( wire sound; gameandwatch gameandwatch ( - .clk_sys_131_072(clk_sys_131_072), - .clk_vid_32_768 (clk_vid_32_768), + .clk_sys_99_287(clk_sys_99_287), + .clk_vid_33_095(clk_vid_33_095), .reset(~reset_n_s || external_reset_s), .pll_core_locked(pll_core_locked_s), @@ -630,8 +630,8 @@ module core_top ( wire de; wire [23:0] rgb; - assign video_rgb_clock = clk_vid_32_768; - assign video_rgb_clock_90 = clk_vid_32_768_90deg; + assign video_rgb_clock = clk_vid_33_095; + assign video_rgb_clock_90 = clk_vid_33_095_90deg; assign video_rgb = de ? rgb : 24'h0; assign video_de = de; assign video_skip = 0; @@ -647,7 +647,7 @@ module core_top ( .CHANNEL_WIDTH(15) ) sound_i2s ( .clk_74a (clk_74a), - .clk_audio(clk_sys_131_072), + .clk_audio(clk_sys_99_287), .audio_l(audio_l), .audio_r(audio_l), @@ -660,9 +660,9 @@ module core_top ( //////////////////////////////////////////////////////////////////////////////////////// // PLL - wire clk_sys_131_072; - wire clk_vid_32_768; - wire clk_vid_32_768_90deg; + wire clk_sys_99_287; + wire clk_vid_33_095; + wire clk_vid_33_095_90deg; wire pll_core_locked; wire pll_core_locked_s74; @@ -676,9 +676,9 @@ module core_top ( .refclk(clk_74a), .rst (0), - .outclk_0(clk_sys_131_072), - .outclk_1(clk_vid_32_768), - .outclk_2(clk_vid_32_768_90deg), + .outclk_0(clk_sys_99_287), + .outclk_1(clk_vid_33_095), + .outclk_2(clk_vid_33_095_90deg), .locked(pll_core_locked) );