diff --git a/docs/common_errors.md b/docs/common_errors.md
index 29b57d7..e8c440c 100644
--- a/docs/common_errors.md
+++ b/docs/common_errors.md
@@ -1,3 +1,5 @@
 # Common Errors and Gotchas
 
-* When skipping an instruction, the CPU takes the same amount of time as the full instruction. This means that skipping two byte instructions takes 4 cycles
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+* When skipping an instruction, the CPU takes the same amount of time as the full instruction. This means that skipping two byte instructions takes 4 cycles
+* Input for multiple active `S` lines are ORed together
+  * Sometimes one of these lines is grounded and always active, which is also ORed
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diff --git a/docs/registers.md b/docs/registers.md
index 2c84239..d8cb2c9 100644
--- a/docs/registers.md
+++ b/docs/registers.md
@@ -57,4 +57,6 @@ Hardware registers for maintaining stack depth and values. `S` is the first leve
 
 * `H` - 4 bits - Controls which bit (out of 4) for each word in display memory is being used to drive the segments. Docs say it has a 1/4 duty cycle, so each bit is high 1/4th of the time, so it's driven by a counter up to 4. An aside lists the frame frequency as 64Hz
 * `S` - 8 bits - Directly driven by the `W` register (the SM510 docs talk about the `W'` register and `PTW` instruction, but those don't exist on this hardware)
+  * Each bit selects a row of the input matrix, and multiple set bits means the matrix lines are ORed together
+  * Sometimes hardware grounds one of the lines, so it is always active and ORed to the rest of the active input
 * `BS` - 1 bit - Somehow driven by "the contents of the `L` or `Y` register", but it doesn't describe how. It uses the same 1/4 duty cycle, so assumedly it changes along with `H`. MAME ANDs the two registers, but only sometime. TODO: This is implemented with only `L` at the moment
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