mirror of
https://github.com/MiSTer-devel/GBA_MiSTer.git
synced 2026-04-26 03:04:26 +00:00
215 lines
9.6 KiB
VHDL
215 lines
9.6 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.pRegmap_gba.all;
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use work.pProc_bus_gba.all;
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use work.pReg_savestates.all;
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entity gba_timer_module is
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generic
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(
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is_simu : std_logic;
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index : integer;
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Reg_L : regmap_type;
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Reg_H_Prescaler : regmap_type;
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Reg_H_Count_up : regmap_type;
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Reg_H_Timer_IRQ_Enable : regmap_type;
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Reg_H_Timer_Start_Stop : regmap_type
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);
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port
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(
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clk : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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savestate_bus : in proc_bus_gb_type;
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ss_wired_out : out std_logic_vector(proc_buswidth-1 downto 0) := (others => '0');
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ss_wired_done : out std_logic;
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loading_savestate : in std_logic;
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gb_bus : in proc_bus_gb_type;
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wired_out : out std_logic_vector(proc_buswidth-1 downto 0) := (others => '0');
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wired_done : out std_logic;
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prescaleCounter : in unsigned(9 downto 0);
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countup_in : in std_logic;
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tick : out std_logic := '0';
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IRP_Timer : out std_logic := '0';
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debugout : out unsigned(15 downto 0)
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);
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end entity;
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architecture arch of gba_timer_module is
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signal L_Counter_Reload : std_logic_vector(Reg_L .upper downto Reg_L .lower) := (others => '0');
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signal H_Prescaler : std_logic_vector(Reg_H_Prescaler .upper downto Reg_H_Prescaler .lower) := (others => '0');
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signal H_Count_up : std_logic_vector(Reg_H_Count_up .upper downto Reg_H_Count_up .lower) := (others => '0');
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signal H_Timer_IRQ_Enable : std_logic_vector(Reg_H_Timer_IRQ_Enable.upper downto Reg_H_Timer_IRQ_Enable.lower) := (others => '0');
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signal H_Timer_Start_Stop : std_logic_vector(Reg_H_Timer_Start_Stop.upper downto Reg_H_Timer_Start_Stop.lower) := (others => '0');
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signal L_Counter_Reload_writeValue : std_logic_vector(Reg_L .upper downto Reg_L .lower) := (others => '0');
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signal H_Prescaler_writeValue : std_logic_vector(Reg_H_Prescaler .upper downto Reg_H_Prescaler .lower) := (others => '0');
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signal H_Timer_Start_Stop_writeValue : std_logic_vector(Reg_H_Timer_Start_Stop.upper downto Reg_H_Timer_Start_Stop.lower) := (others => '0');
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signal L_Counter_Reload_writeTo : std_logic;
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signal H_Timer_Start_Stop_writeTo : std_logic;
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type t_reg_wired_or is array(0 to 4) of std_logic_vector(31 downto 0);
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signal reg_wired_or : t_reg_wired_or;
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signal reg_wired_done : unsigned(0 to 4);
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signal counter_readback : std_logic_vector(15 downto 0) := (others => '0');
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signal counter : unsigned(15 downto 0) := (others => '0');
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signal newCounter : unsigned(16 downto 0);
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signal prescaleMask : unsigned(9 downto 0);
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signal timer_on : std_logic := '0';
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signal startwait : std_logic := '0';
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-- savestate
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signal SAVESTATE_TIMER : std_logic_vector(29 downto 0);
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signal SAVESTATE_TIMER_BACK : std_logic_vector(29 downto 0);
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signal debugout_next : unsigned(15 downto 0) := (others => '0');
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begin
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SAVESTATE_TIMER_BACK(0) <= timer_on;
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SAVESTATE_TIMER_BACK(1) <= '0';
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SAVESTATE_TIMER_BACK(18 downto 2) <= '0' & std_logic_vector(counter);
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SAVESTATE_TIMER_BACK(29 downto 19) <= '0' & std_logic_vector(prescalecounter) when (index = 0) else (others => '0');
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iSAVESTATE_TIMER : entity work.eProcReg_gba generic map (REG_SAVESTATE_TIMER, index) port map (clk, savestate_bus, ss_wired_out, ss_wired_done, SAVESTATE_TIMER_BACK, SAVESTATE_TIMER);
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iL_Counter_Reload : entity work.eProcReg_gba generic map ( Reg_L ) port map (clk, gb_bus, reg_wired_or(0), reg_wired_done(0), counter_readback , L_Counter_Reload , open, L_Counter_Reload_writeValue , L_Counter_Reload_writeTo);
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iH_Prescaler : entity work.eProcReg_gba generic map ( Reg_H_Prescaler ) port map (clk, gb_bus, reg_wired_or(1), reg_wired_done(1), H_Prescaler , H_Prescaler , open, H_Prescaler_writeValue);
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iH_Count_up : entity work.eProcReg_gba generic map ( Reg_H_Count_up ) port map (clk, gb_bus, reg_wired_or(2), reg_wired_done(2), H_Count_up , H_Count_up );
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iH_Timer_IRQ_Enable : entity work.eProcReg_gba generic map ( Reg_H_Timer_IRQ_Enable ) port map (clk, gb_bus, reg_wired_or(3), reg_wired_done(3), H_Timer_IRQ_Enable , H_Timer_IRQ_Enable);
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iH_Timer_Start_Stop : entity work.eProcReg_gba generic map ( Reg_H_Timer_Start_Stop ) port map (clk, gb_bus, reg_wired_or(4), reg_wired_done(4), H_Timer_Start_Stop , H_Timer_Start_Stop , open, H_Timer_Start_Stop_writeValue, H_Timer_Start_Stop_writeTo );
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process (reg_wired_or)
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variable wired_or : std_logic_vector(31 downto 0);
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begin
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wired_or := reg_wired_or(0);
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for i in 1 to (reg_wired_or'length - 1) loop
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wired_or := wired_or or reg_wired_or(i);
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end loop;
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wired_out <= wired_or;
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end process;
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wired_done <= '0' when (reg_wired_done = 0) else '1';
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prescaleMask <= 10x"001" when H_Prescaler = "00" else
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10x"03F" when H_Prescaler = "01" else
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10x"0FF" when H_Prescaler = "10" else
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10x"3FF";
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process (all)
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begin
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newCounter <= '0' & counter;
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if (timer_on = '1' and startwait = '0') then
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if (H_Count_up = "0" or index = 0) then
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if (H_Prescaler = "00" or ((prescaleCounter and prescaleMask) = prescaleMask)) then
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newCounter <= resize(counter, newCounter'length) + 1;
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end if;
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elsif (H_Count_up = "1" and countup_in = '1') then
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newCounter <= resize(counter, newCounter'length) + 1;
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end if;
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end if;
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end process;
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process (all)
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begin
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tick <= '0';
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IRP_Timer <= '0';
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if (startwait = '1') then
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if (counter = x"FFFF" and H_Timer_IRQ_Enable = "1") then
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IRP_Timer <= '1';
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end if;
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end if;
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if (timer_on = '1' and startwait = '0') then
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if (newCounter(16) = '1') then
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tick <= '1';
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if (H_Timer_IRQ_Enable = "1") then
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IRP_Timer <= '1';
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end if;
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end if;
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end if;
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end process;
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process (clk)
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begin
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if rising_edge(clk) then
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debugout_next <= unsigned(counter_readback);
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debugout <= debugout_next;
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if (reset = '1') then
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timer_on <= SAVESTATE_TIMER(0);
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counter <= unsigned(SAVESTATE_TIMER(17 downto 2));
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elsif (ce = '1') then
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if (startwait = '1') then
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startwait <= '0';
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counter <= unsigned(L_Counter_Reload);
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counter_readback <= L_Counter_Reload;
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end if;
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if (timer_on = '1' and startwait = '0') then
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counter <= newCounter(15 downto 0);
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counter_readback <= std_logic_vector(newCounter(15 downto 0));
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if (newCounter(16) = '1') then
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counter <= unsigned(L_Counter_Reload);
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counter_readback <= L_Counter_Reload;
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end if;
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end if;
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-- set_settings
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if (H_Timer_Start_Stop_writeTo = '1' and loading_savestate = '0') then
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timer_on <= H_Timer_Start_Stop_writeValue(H_Timer_Start_Stop'left);
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if (H_Timer_Start_Stop_writeValue = "1" and timer_on = '0') then
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if (H_Prescaler_writeValue = "00") then
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startwait <= '1';
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else
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if (L_Counter_Reload_writeTo = '1') then
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counter <= unsigned(L_Counter_Reload_writeValue);
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counter_readback <= L_Counter_Reload_writeValue;
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else
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counter <= unsigned(L_Counter_Reload);
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counter_readback <= L_Counter_Reload;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end architecture;
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