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79 lines
1.7 KiB
Verilog
79 lines
1.7 KiB
Verilog
`timescale 1ps / 1ps
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//-------------------------------------------------------------------------------------------------
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module cpu
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//-------------------------------------------------------------------------------------------------
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(
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input wire clock,
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input wire cep,
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input wire cen,
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input wire reset,
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output wire rfsh,
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output wire mreq,
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output wire iorq,
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input wire nmi,
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output wire wr,
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output wire rd,
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output wire m1,
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input wire[ 7:0] d,
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output wire[ 7:0] q,
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output wire[15:0] a
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);
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//-------------------------------------------------------------------------------------------------
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`ifdef VERILATOR
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tv80e Z80CPU (
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.m1_n(m1),
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.mreq_n(mreq),
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.iorq_n(iorq),
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.rd_n(rd),
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.wr_n(wr),
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.rfsh_n(rfsh),
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.halt_n(),
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.busak_n(),
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.A(a),
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.dout(q),
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.reset_n(reset),
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.clk(clock),
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.cen(cen),
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.wait_n(1'b1),
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.int_n(1'b1),
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.nmi_n(nmi),
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.busrq_n(1'b1),
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.di(d),
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.dir(1'b0),
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.dirset(212'd0)
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);
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`else
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T80pa Cpu
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(
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.CLK (clock),
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.CEN_p (cep ),
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.CEN_n (cen ),
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.RESET_n(reset),
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.BUSRQ_n(1'b1 ),
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.WAIT_n (1'b1 ),
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.BUSAK_n( ),
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.HALT_n ( ),
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.RFSH_n (rfsh ),
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.MREQ_n (mreq ),
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.IORQ_n (iorq ),
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.NMI_n (nmi ),
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.INT_n (1'b1 ),
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.WR_n (wr ),
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.RD_n (rd ),
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.M1_n (m1 ),
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.DI (d ),
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.DO (q ),
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.A (a ),
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.OUT0 (1'b0 ),
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.REG ( ),
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.DIRSet (1'b0 ),
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.DIR (212'd0)
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);
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`endif
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//-------------------------------------------------------------------------------------------------
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endmodule
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//-------------------------------------------------------------------------------------------------
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