mirror of
https://github.com/MiSTer-devel/EDSAC_MiSTer.git
synced 2026-04-19 03:04:19 +00:00
cbd9d1d69b
Matched the file naming scheme and file structure to that of the other repos for cores, so as to fix an issue with scripts that require specific names. https://github.com/MiSTer-devel/Updater_script_MiSTer/issues/59#issuecomment-781639064
494 lines
15 KiB
Verilog
494 lines
15 KiB
Verilog
// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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/* Charset contains EDSAC charset, applied from a font like the one on a IBM Model B typewriter */
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module teletype_charset (
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address,
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clock,
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q);
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input [10:0] address;
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input clock;
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output [15:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [15:0] sub_wire0;
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wire [15:0] q = sub_wire0[15:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_a ({16{1'b1}}),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_a (1'b0),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_a = "NONE",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.init_file = "./roms/edsac_charset.mif",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 2048,
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altsyncram_component.operation_mode = "ROM",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.ram_block_type = "M10K",
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altsyncram_component.widthad_a = 11,
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altsyncram_component.width_a = 16,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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/* Terminal frame buffer, contains 64 x 32 characters which correspond to letters on teletype emulator screen */
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module teletype_fb (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [5:0] data;
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input [10:0] rdaddress;
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input [10:0] wraddress;
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input wren;
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output [5:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [5:0] sub_wire0;
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wire [5:0] q = sub_wire0[5:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({6{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 2048,
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altsyncram_component.numwords_b = 2048,
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altsyncram_component.init_file = "./roms/blank_textbuffer.mif",
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 11,
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altsyncram_component.widthad_b = 11,
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altsyncram_component.width_a = 6,
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altsyncram_component.width_b = 6,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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/* Sounds buffer, contains ADPCM encoded sound effects */
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module sound_lib (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [3:0] data;
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input [15:0] rdaddress;
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input [15:0] wraddress;
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input wren;
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output [3:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [3:0] sub_wire0;
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wire [3:0] q = sub_wire0[3:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({4{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 65535,
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altsyncram_component.numwords_b = 65535,
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altsyncram_component.init_file = "./roms/sound_library.mif",
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 16,
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altsyncram_component.widthad_b = 16,
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altsyncram_component.width_a = 4,
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altsyncram_component.width_b = 4,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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/* Temporary storage to hold tape images uploaded from the SD card until EDSAC processes them */
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module edsac_tape_ram (
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address_a,
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address_b,
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clock_a,
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clock_b,
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data_a,
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data_b,
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wren_a,
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wren_b,
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q_a,
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q_b);
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input [11:0] address_a;
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input [11:0] address_b;
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input clock_a;
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input clock_b;
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input [7:0] data_a;
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input [7:0] data_b;
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input wren_a;
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input wren_b;
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output [7:0] q_a;
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output [7:0] q_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock_a;
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tri0 wren_a;
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tri0 wren_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] sub_wire1;
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// wire [7:0] q_a = sub_wire0[7:0];
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wire [7:0] q_a = sub_wire0[7:0];
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wire [7:0] q_b = sub_wire1[7:0] ^ 5'b10000;
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.clock0 (clock_a),
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.clock1 (clock_b),
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.data_a (data_a),
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.data_b (data_b),
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.wren_a (wren_a),
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.wren_b (wren_b),
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.q_a (sub_wire0),
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.q_b (sub_wire1),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1));
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defparam
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.indata_reg_b = "CLOCK1",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.init_file = "./roms/blank_tape_ram.mif",
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altsyncram_component.numwords_a = 4096,
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altsyncram_component.numwords_b = 4096,
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.outdata_reg_b = "CLOCK1",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 12,
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altsyncram_component.widthad_b = 12,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_b = 8,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
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endmodule
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/* Stores compressed background images for scope and panel.
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Supports writing from userspace as well to prevent recompile when tweaking the images */
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module image_library (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [7:0] data;
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input [16:0] rdaddress;
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input [16:0] wraddress;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({8{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.init_file = "./roms/rle_combined.mif",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 131072,
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altsyncram_component.numwords_b = 131072,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 17,
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altsyncram_component.widthad_b = 17,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_b = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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/* Main EDSAC memory */
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module edsac_memory (
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address_a,
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address_b,
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byteena_a,
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byteena_b,
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clock_a,
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clock_b,
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data_a,
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data_b,
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wren_a,
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wren_b,
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q_a,
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q_b);
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input [8:0] address_a;
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input [8:0] address_b;
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input [3:0] byteena_a;
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input [3:0] byteena_b;
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input clock_a;
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input clock_b;
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input [35:0] data_a;
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input [35:0] data_b;
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input wren_a;
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input wren_b;
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output [35:0] q_a;
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output [35:0] q_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 [3:0] byteena_a;
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tri1 [3:0] byteena_b;
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tri1 clock_a;
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tri0 wren_a;
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tri0 wren_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [35:0] sub_wire0;
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wire [35:0] sub_wire1;
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wire [35:0] q_a = sub_wire0[35:0];
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wire [35:0] q_b = sub_wire1[35:0];
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.byteena_a (byteena_a),
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.byteena_b (byteena_b),
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.clock0 (clock_a),
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.clock1 (clock_b),
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.data_a (data_a),
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.data_b (data_b),
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.wren_a (wren_a),
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.wren_b (wren_b),
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.q_a (sub_wire0),
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.q_b (sub_wire1),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1));
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defparam
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.byteena_reg_b = "CLOCK1",
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altsyncram_component.byte_size = 9,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.indata_reg_b = "CLOCK1",
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altsyncram_component.init_file = "./roms/initial_v2.mif",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 512,
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altsyncram_component.numwords_b = 512,
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.outdata_reg_b = "CLOCK1",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 9,
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altsyncram_component.widthad_b = 9,
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altsyncram_component.width_a = 36,
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altsyncram_component.width_b = 36,
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altsyncram_component.width_byteena_a = 4,
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altsyncram_component.width_byteena_b = 4,
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
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|
|
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endmodule
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