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cbd9d1d69b
Matched the file naming scheme and file structure to that of the other repos for cores, so as to fix an issue with scripts that require specific names. https://github.com/MiSTer-devel/Updater_script_MiSTer/issues/59#issuecomment-781639064
11 lines
160 B
Verilog
11 lines
160 B
Verilog
module random (
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input clock,
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output reg [30:0] lfsr
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);
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always @(posedge clock) begin
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lfsr <= {lfsr[29:0], lfsr[30] ^~ lfsr[27]};
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end
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endmodule
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