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104 lines
2.8 KiB
Verilog
104 lines
2.8 KiB
Verilog
// approximate step a 3-vector direction a given distance
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// only uses the msb of the distance to avoid a full multiply
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// we're going to iterate this a few times, so we can afford to be a bit sloppy
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// and save a ton of gate area
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// the operation performed here is approximately:
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// xyzout = d*xyzin >> 14
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module step3vec (
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input signed [10:0] d,
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input signed [15:0] xin_,
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input signed [15:0] yin_,
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input signed [15:0] zin_,
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output reg signed [15:0] xout,
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output reg signed [15:0] yout,
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output reg signed [15:0] zout
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);
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wire sd = d[10];
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wire [9:0] dabs = sd ? ~d[9:0] : d[9:0];
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wire [15:0] xin = sd ? ~xin_ : xin_;
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wire [15:0] yin = sd ? ~yin_ : yin_;
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wire [15:0] zin = sd ? ~zin_ : zin_;
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wire _unused_ok = &{xin_[4:0], yin_[4:0], zin_[4:0], xin[4:0], yin[4:0], zin[4:0]};
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wire sx = xin[15];
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wire sy = yin[15];
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wire sz = zin[15];
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always @* begin
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casez (dabs)
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10'b1?????????: // (xin << 9) >> 14 = xin >> 5
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begin
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xout = {{6{sx}}, xin[14:5]};
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yout = {{6{sy}}, yin[14:5]};
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zout = {{6{sz}}, zin[14:5]};
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end
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10'b01????????: // (xin << 8) >> 14 = xin >> 6
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begin
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xout = {{7{sx}}, xin[14:6]};
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yout = {{7{sy}}, yin[14:6]};
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zout = {{7{sz}}, zin[14:6]};
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end
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10'b001???????: // (xin << 7) >> 14 = xin >> 7
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begin
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xout = {{8{sx}}, xin[14:7]};
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yout = {{8{sy}}, yin[14:7]};
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zout = {{8{sz}}, zin[14:7]};
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end
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10'b0001??????: // (xin << 6) >> 14 = xin >> 8
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begin
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xout = {{9{sx}}, xin[14:8]};
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yout = {{9{sy}}, yin[14:8]};
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zout = {{9{sz}}, zin[14:8]};
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end
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10'b00001?????: // (xin << 5) >> 14 = xin >> 9
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begin
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xout = {{10{sx}}, xin[14:9]};
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yout = {{10{sy}}, yin[14:9]};
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zout = {{10{sz}}, zin[14:9]};
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end
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10'b000001????: // (xin << 4) >> 14 = xin >> 10
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begin
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xout = {{11{sx}}, xin[14:10]};
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yout = {{11{sy}}, yin[14:10]};
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zout = {{11{sz}}, zin[14:10]};
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end
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10'b0000001???: // (xin << 3) >> 14 = xin >> 11
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begin
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xout = {{12{sx}}, xin[14:11]};
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yout = {{12{sy}}, yin[14:11]};
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zout = {{12{sz}}, zin[14:11]};
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end
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10'b00000001??: // (xin << 2) >> 14 = xin >> 12
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begin
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xout = {{13{sx}}, xin[14:12]};
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yout = {{13{sy}}, yin[14:12]};
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zout = {{13{sz}}, zin[14:12]};
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end
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10'b000000001?: // (xin << 1) >> 14 = xin >> 13
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begin
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xout = {{14{sx}}, xin[14:13]};
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yout = {{14{sy}}, yin[14:13]};
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zout = {{14{sz}}, zin[14:13]};
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end
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10'b0000000001: // (xin << 0) >> 14 = xin >> 14
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begin
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xout = {{15{sx}}, xin[14]};
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yout = {{15{sy}}, yin[14]};
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zout = {{15{sz}}, zin[14]};
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end
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default:
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begin
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xout = 16'b0;
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yout = 16'b0;
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zout = 16'b0;
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end
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endcase
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end
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endmodule
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