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31 lines
468 B
Verilog
31 lines
468 B
Verilog
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module ram (
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input clk,
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input [14:0] addr,
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input [7:0] din,
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input we,
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input cs,
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output reg [7:0] dout,
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// port b
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input [14:0] addr_b,
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output reg [7:0] dout_b
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);
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reg [7:0] memory[32767:0];
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`ifdef XILINX_ISIM
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reg [14:0] ii;
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initial begin
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for (ii = 0; ii < 32767; ii = ii + 1) memory[ii] = 0;
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end
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`endif
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always @(posedge clk) begin
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if (~we && ~cs) memory[addr] <= din;
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dout <= memory[addr];
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dout_b <= memory[addr_b];
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end
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endmodule
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