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99 lines
1.6 KiB
Verilog
99 lines
1.6 KiB
Verilog
/* FPGA Util library
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Copyright (C) 2013-2014 Carsten Elton Sorensen
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module util_dff(
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input clk,
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input res,
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input d,
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output reg q
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);
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always @(posedge clk or posedge res)
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if(res)
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q <= 1'b0;
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else
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q <= d;
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endmodule
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// Synchronizes an asynchronous signal d to clk. The pulse width of d must be larger than clk
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module util_sync_domain(
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input clk,
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input d,
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output reg q
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);
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reg delayed;
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always @(posedge clk) begin
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q <= delayed;
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delayed <= d;
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end
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endmodule
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module util_delay(
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input clk,
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input res,
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input in,
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input res_in,
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output reg out
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);
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always @(posedge clk or posedge res)
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if(res) begin
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out <= res_in;
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end else begin
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out <= in;
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end
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endmodule
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module util_posedge(
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input clk,
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input res,
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input in,
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output out
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);
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wire in_delay;
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util_delay delay(clk, res, in, in, in_delay);
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assign out = in && !in_delay;
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endmodule
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module util_negedge(
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input clk,
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input res,
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input in,
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output out
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);
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wire in_delay;
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util_delay delay(clk, res, in, in, in_delay);
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assign out = !in && in_delay;
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endmodule
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