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61 lines
1.6 KiB
Verilog
Executable File
61 lines
1.6 KiB
Verilog
Executable File
/* FPGA Util library
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Copyright (C) 2013 Carsten Elton Sorensen
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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// "BCD" encoder. Generates the hundreds, tens and ones digits
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module bcd(
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input [7:0] in,
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output [1:0] out1,
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output [3:0] out2,
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output [3:0] out3
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);
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wire [7:0] hundreds;
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assign {out1,hundreds} =
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in >= 200 ? {2'd2, 8'd200} :
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in >= 100 ? {2'd1, 8'd100} :
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{2'd0, 8'd0};
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wire [6:0] h_rem = in - hundreds;
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wire [6:0] tens;
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assign {out2,tens} =
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h_rem >= 90 ? {4'd9, 7'd90} :
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h_rem >= 80 ? {4'd8, 7'd80} :
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h_rem >= 70 ? {4'd7, 7'd70} :
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h_rem >= 60 ? {4'd6, 7'd60} :
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h_rem >= 50 ? {4'd5, 7'd50} :
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h_rem >= 40 ? {4'd4, 7'd40} :
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h_rem >= 30 ? {4'd3, 7'd30} :
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h_rem >= 20 ? {4'd2, 7'd20} :
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h_rem >= 10 ? {4'd1, 7'd10} :
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{4'd0, 7'd0};
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wire [3:0] t_rem = h_rem - tens;
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assign out3 =
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t_rem >= 9 ? 4'd9 :
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t_rem >= 8 ? 4'd8 :
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t_rem >= 7 ? 4'd7 :
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t_rem >= 6 ? 4'd6 :
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t_rem >= 5 ? 4'd5 :
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t_rem >= 4 ? 4'd4 :
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t_rem >= 3 ? 4'd3 :
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t_rem >= 2 ? 4'd2 :
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t_rem >= 1 ? 4'd1 :
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4'd0;
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endmodule
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