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https://github.com/MiSTer-devel/Chip8_MiSTer.git
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146 lines
2.9 KiB
Verilog
Executable File
146 lines
2.9 KiB
Verilog
Executable File
/* FPGA Chip-8
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Copyright (C) 2013 Carsten Elton S<>rensen
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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`include "blitter.vh"
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module nexys3_top(
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input clk,
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input [4:0] btn,
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input [7:0] sw,
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inout PS2KeyboardData,
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inout PS2KeyboardClk,
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output [2:0] vgaRed,
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output [2:0] vgaGreen,
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output [2:1] vgaBlue,
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output Hsync,
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output Vsync,
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output [7:0] seg,
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output [3:0] an
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);
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assign PS2KeyboardData = 1'bZ;
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assign PS2KeyboardClk = 1'bZ;
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wire vgaClk;
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wire audio_enable;
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wire error;
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// VGA clock
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DCM_CLKGEN #(
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.CLKFXDV_DIVIDE(2), // CLKFXDV divide value (2, 4, 8, 16, 32)
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.CLKFX_DIVIDE(163), // Divide value - D - (1-256)
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.CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis
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.CLKFX_MULTIPLY(41), // Multiply value - M - (2-256)
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.CLKIN_PERIOD(10.0), // Input clock period specified in nS
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.SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
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// "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
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.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
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)
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VGAClock (
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.CLKFX(vgaClk), // 1-bit output: Generated clock output
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.CLKIN(clk), // 1-bit input: Input clock
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.RST(1'b0) // 1-bit input: Reset input pin
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);
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// CPU clock
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wire cpu_clk;
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clk_divider #(.divider(5000)) Clock_20kHz(
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1'b0,
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clk,
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cpu_clk);
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wire clk_1khz;
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clk_divider #(.divider(100000)) Clock_1kHz(
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1'b0,
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clk,
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clk_1khz);
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// Hex segment
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wire [15:0] hexdigits;
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hex_segment_driver HexDriver(
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clk_1khz,
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hexdigits[15:12], 1'b1,
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hexdigits[11:8], 1'b1,
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hexdigits[7:4], 1'b1,
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hexdigits[3:0], 1'b1,
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seg, an);
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// Buttons
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wire [4:0] btn_down, btn_down_edge;
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five_way_buttons Buttons(
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.clk(clk_1khz),
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.but(btn),
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.down(btn_down),
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.down_edge(btn_down_edge));
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// CPU single stepping
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reg run = 1'd0;
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reg run_prev = 1'd0;
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wire halt = !(run && !run_prev);
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always @ (posedge cpu_clk) begin
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run_prev <= run;
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end
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always @ (posedge clk_1khz) begin
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run <= btn_down_edge[0];
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end
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chip8 chip8machine(
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1'b0, //res
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vgaClk,
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cpu_clk,
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clk,
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halt && sw[7],
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1'b0, //wide
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Hsync, Vsync,
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vgaRed, vgaGreen, vgaBlue,
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hexdigits,
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audio_enable,
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PS2KeyboardData, PS2KeyboardClk,
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1'b0,
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1'b0,
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1'b0,
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12'b0, 8'b0,
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error
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);
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endmodule
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