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46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
/* FPGA Chip-8
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Copyright (C) 2013-2014 Carsten Elton Sorensen
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module framebuffer(
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input vga_clk,
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input [8:0] vga_addr,
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output reg [15:0] vga_out,
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input clk,
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input fbuf_en,
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input fbuf_write,
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input [8:0] fbuf_addr,
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input [15:0] fbuf_in,
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output reg [15:0] fbuf_out
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);
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reg [15:0] ram [0:511];
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always @(posedge clk) begin
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if (fbuf_en) begin
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if (fbuf_write)
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ram[fbuf_addr] <= fbuf_in;
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else
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fbuf_out <= ram[fbuf_addr];
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end
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end
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always @(posedge vga_clk)
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vga_out <= ram[vga_addr];
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endmodule
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