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72 lines
2.1 KiB
Verilog
Executable File
72 lines
2.1 KiB
Verilog
Executable File
/* FPGA Chip-8
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Copyright (C) 2013-2014 Carsten Elton Sorensen
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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// The Chip-8 CPU's dual port memory
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module cpu_memory(
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input a_clk,
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input a_en,
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input a_write,
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output reg [7:0] a_data_out,
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input [7:0] a_data_in,
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input [11:0] a_addr,
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input b_clk,
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output reg [7:0] b_data,
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input [11:0] b_addr
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);
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reg [7:0] ram [0:4095];
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initial begin
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$readmemh("../rom/font_large.vh", ram, 0, 255);
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$readmemh("../rom/font_small.vh", ram, 256, 383);
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$readmemh("../rom/reset.vh", ram, 384);
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// $readmemh("../rom/title.vh", ram, 512);
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$readmemh("../rom/logo.vh", ram, 512);
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// $readmemh("../games/addition.vh", ram, 512);
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// $readmemh("../games/alien.vh", ram, 512);
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// $readmemh("../games/ant.vh", ram, 512);
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// $readmemh("../games/blinky.vh", ram, 512);
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// $readmemh("../games/car.vh", ram, 512);
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// $readmemh("../games/field.vh", ram, 512);
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// $readmemh("../games/hpiper.vh", ram, 512);
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// $readmemh("../games/joust.vh", ram, 512);
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// $readmemh("../games/laser.vh", ram, 512);
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// $readmemh("../games/loopz.vh", ram, 512);
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// $readmemh("../games/pong.vh", ram, 512);
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// $readmemh("../games/fontdump.vh", ram, 512);
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// $readmemh("../games/rpltest.vh", ram, 512);
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end
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always @(posedge a_clk)
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if (a_en) begin
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// Write protect the lower 512 bytes (charset)
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if (a_write) begin
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if (|a_addr[11:9])
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ram[a_addr] <= a_data_in;
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end else begin
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a_data_out <= ram[a_addr];
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end
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end
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always @(posedge b_clk)
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b_data <= ram[b_addr];
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endmodule
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