mirror of
https://github.com/MiSTer-devel/Chip8_MiSTer.git
synced 2026-05-17 03:03:28 +00:00
384 lines
8.3 KiB
Systemverilog
384 lines
8.3 KiB
Systemverilog
/********************************************************/
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/* Chip8.sv */
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/* Original core by Carsten Elton Sørensen */
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/* Ported from MiST to MiSTer by Paul Sajna (sajattack) */
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/********************************************************/
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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`include "build_id.v"
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localparam CONF_STR = {
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"Chip8;;",
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"-;",
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"F,CH8;",
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"-;",
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"O4,Aspect ratio,4:3,16:9;",
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"O8A,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"-;",
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"O2,CPU Speed,Fast,Slow;",
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"-;",
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"R0,Reset;",
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//"J,",
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"V,v",`BUILD_DATE
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};
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wire [31:0] status;
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wire forced_scandoubler;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_data;
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wire [7:0] ioctl_index;
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wire ioctl_download;
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wire ioctl_wait;
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//wire [10:0] ps2_key;
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wire [1:0] buttons;
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wire [21:0] gamma_bus;
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wire [14:0] ldata, rdata;
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wire ps2_clk;
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wire [7:0] ps2_dat;
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hps_io #(.CONF_STR(CONF_STR),.PS2DIV(4000)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_data),
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.ioctl_wait(ioctl_wait),
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.forced_scandoubler(forced_scandoubler),
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.buttons(buttons),
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.status(status),
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.ps2_kbd_clk_out(ps2_clk),
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.ps2_kbd_data_out(ps2_dat)
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);
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reg [4:0] audio_count;
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always @(posedge clk_12k)
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audio_count <= audio_count + 1'b1;
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wire audio_enable;
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wire audio = audio_enable && &audio_count[4:3];
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assign AUDIO_R = audio ? 16'h2000: 16'h0000;
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assign AUDIO_L = audio ? 16'h2000: 16'h0000;
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assign AUDIO_S = 0;
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assign AUDIO_MIX = 0;
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assign LED_POWER = 0;
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assign LED_DISK = 0;
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assign LED_USER = ioctl_download;
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assign VIDEO_ARX = status[4] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[4] ? 8'd9 : 8'd3;
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assign CE_PIXEL = 1'b1;
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wire [2:0] scale = status[10:8];
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wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
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assign VGA_SL = sl[1:0];
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign HDMI_BOB_DEINT = 0;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CKE, SDRAM_CLK, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign USER_OUT = '1;
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assign ADC_BUS = 'Z;
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assign BUTTONS = 0;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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wire clk_sys; // 50MHz
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wire clk_cpu_fast, clk_cpu_slow; // 12.5KHz or 5KHz
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wire clk_video; // 13.5MHz
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wire clk_12k; // 12 KHz
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wire clk_1m; // 1MHz, for dividing into the required smaller amounts
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wire locked;
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wire cpu_clk;
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wire error;
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pll pll
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(
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.refclk(CLK_50M),
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.outclk_0(clk_video),
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.outclk_1(clk_1m),
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.locked(locked)
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);
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reg [6:0] clkdiv_12_5_count;
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always @(posedge clk_1m) begin
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clkdiv_12_5_count <= clkdiv_12_5_count + 7'd1;
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if (clkdiv_12_5_count == 79) begin
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clk_cpu_fast <= ~clk_cpu_fast;
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clkdiv_12_5_count <= 0;
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end
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end
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reg [6:0] clkdiv_12_count;
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always @(posedge clk_1m) begin
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clkdiv_12_count <= clkdiv_12_count + 7'd1;
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if (clkdiv_12_count == 82) begin // should be 82 + 1/3 but yolo
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clk_12k <= ~clk_12k;
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clkdiv_12_count <= 0;
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end
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end
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reg [7:0] clkdiv_5_count;
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always @(posedge clk_1m) begin
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clkdiv_5_count <= clkdiv_5_count + 8'd1;
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if (clkdiv_5_count == 199) begin
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clk_cpu_slow <= ~clk_cpu_slow;
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clkdiv_5_count <= 0;
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end
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end
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assign clk_sys = CLK_50M;
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assign CLK_VIDEO = clk_video;
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assign cpu_clk = status[2] ? clk_cpu_slow : clk_cpu_fast;
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// Reset circuit
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wire error_posedge;
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util_posedge ErrorPosedge(clk_12k, 0, error, error_posedge);
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wire downloading_negedge;
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util_negedge downloadingNegedge(clk_12k, 0, ioctl_download, downloading_negedge);
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wire button1_posedge;
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util_posedge ButtonPosedge(clk_12k, 0, buttons[1] | status[0] | RESET, button1_posedge);
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reg [4:0] reset_count = 0;
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reg reset = 0;
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always @(posedge clk_12k) begin
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if (reset) begin
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if (reset_count[4]) begin
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reset <= 1'b0;
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reset_count <= 0;
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end else begin
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reset_count <= reset_count + 1'b1;
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end;
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end else if (downloading_negedge || button1_posedge || error_posedge) begin
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reset <= 1'b1;
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end;
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end
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// Chip-8 machine
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wire [15:0] current_opcode;
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chip8 chip8machine(
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reset,
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clk_video,
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cpu_clk,
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clk_sys,
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ioctl_download,
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1,
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status[4],
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VGA_HS, VGA_VS,
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VGA_R[5:3], VGA_G[5:3], VGA_B[5:4],
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VGA_DE,
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current_opcode,
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audio_enable,
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ps2_dat,
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ps2_clk,
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ioctl_download,
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ioctl_wr,
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clk_sys,
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ioctl_addr[11:0] + 12'd512,
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ioctl_data,
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error
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);
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endmodule
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