mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-06-14 03:04:32 +00:00
2b2c222d82
- Remount is allowed without reset, when the CD wasn't read yet during power cycle - Allows changing a disc with multi disc titles after application induced eject - Added debug option to allow replacing the image during operation - Also fixed tray close on image mount
Verilator Simulation
Verilator is much faster than ModelSim but is restricted to Verilog/SystemVerilog. VHDL source code must be converted first.
Please use the convert scripts in case the VHDL code was changed. To be safe, a conversion is already part of the repo.
Prerequisites
You need CD images to use with the simulation. Only the .bin files are required. .chd is not supported.
Usage
./sim_top.sh