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CDi_MiSTer/sim2
History
Andre Zeps f855ffc493 FMV: Fixed some meta data returned by MV_Status 
- Fixed temporal ref and both frame rate registers
- Effect on commerical titles unknown
2025-12-28 15:49:43 +01:00
..
.clang-format
First public release
2024-07-08 19:22:59 +02:00
.gitignore
Updated MiSTer framework (sys) to da7ddde
2025-09-24 17:31:12 +02:00
byte_word_test.asm
Boot fixes and video implementation
2024-08-17 22:32:51 +02:00
cdic_audiomap.asm
CDIC: Rewritten audio state machine
2025-03-17 21:58:10 +01:00
cdic_cdda_play.asm
CDIC: Rewritten audio state machine
2025-03-17 21:58:10 +01:00
cdic_data.asm
CDIC: Added CD sector cache
2025-10-16 18:07:31 +02:00
cdic_sector_send.asm
CDIC: Add Seek command and subchannel data frame
2024-12-23 02:04:45 +01:00
cdic_xa_play.asm
AD7528: Reduces volume of input to 56%
2025-03-28 19:27:09 +01:00
crc.h
MPEG video decoder synthesizable for MiSTer
2025-09-09 00:06:42 +02:00
create_wav.sh
MPEG Audio is working
2025-07-15 20:49:26 +02:00
hle.h
Simulation: Added syscall analysis
2025-12-15 22:37:24 +01:00
memtest.asm
DVC test with SkyWays
2025-06-11 18:48:11 +02:00
memzero.asm
DVC test with SkyWays
2025-06-11 18:48:11 +02:00
nvram_backup_restore.asm
HPS: Added NvRAM backup and restore
2024-12-12 07:29:13 +01:00
nvramsender.asm
HPS: Added NvRAM backup and restore
2024-12-12 07:29:13 +01:00
pl_mpeg_pc.h
Added simulatable MPEG video decoder
2025-09-08 23:46:32 +02:00
produce_cdi_rom.sh
DVC test with SkyWays
2025-06-11 18:48:11 +02:00
produce_test_rom.sh
FMV: Added support for VCD pixelclock
2025-12-28 15:49:43 +01:00
ramsender.asm
DVC test with SkyWays
2025-06-11 18:48:11 +02:00
rc5_joy_upwards.csv
68HC05: Added Input Capture registers and adjusted clock frequency
2025-04-14 09:54:22 +02:00
README.md
Removed git submodules
2025-11-13 20:12:20 +01:00
romsender.asm
DVC test with SkyWays
2025-06-11 18:48:11 +02:00
scramble.h
MPEG video decoder synthesizable for MiSTer
2025-09-09 00:06:42 +02:00
sim_slave.cpp
First public release
2024-07-08 19:22:59 +02:00
sim_slave.sh
First public release
2024-07-08 19:22:59 +02:00
sim_top.cpp
FMV: Fixed some meta data returned by MV_Status
2025-12-28 15:49:43 +01:00
sim_top.sh
FMV: Added display offset registers
2025-09-29 12:46:40 +02:00
slavetest.asm
68HC05: Added Input Capture registers and adjusted clock frequency
2025-04-14 09:54:22 +02:00
table_of_contents.h
MPEG video decoder synthesizable for MiSTer
2025-09-09 00:06:42 +02:00
tb_slave.sv
First public release
2024-07-08 19:22:59 +02:00
tg68kdotc_verilog_wrapper.v
SCC68070: Removed privilege violation from SR read
2025-11-13 20:11:55 +01:00
uarttest.asm
SCC68070: Fixed UART IRQ handling
2024-11-20 19:33:10 +01:00
unaligned_video_test.asm
MCD212: Added video plane visibility debug option
2024-12-12 17:36:15 +01:00
ur6805.v
Simulation: Verilator update fixes
2025-12-18 13:30:33 +01:00
videosim_top.cpp
FMV: Improved timing of latched offset settings
2025-12-28 15:49:43 +01:00
videosim.sh
FMV: Improved timing of latched offset settings
2025-12-28 15:49:43 +01:00
vmpeg_resume_test.asm
FMA: Fixed decoding flag in status register
2025-11-23 21:10:11 +01:00
vmpeg_scan_test.asm
Altered linker and startup scripts
2025-11-13 19:45:25 +01:00
vmpeg_single_frame_test.asm
FMV: Added support for VCD pixelclock
2025-12-28 15:49:43 +01:00
vmpeg_single_frame_vcd_test.asm
FMV: Added support for VCD pixelclock
2025-12-28 15:49:43 +01:00
vmpegtest.asm
FMV: Fixed some meta data returned by MV_Status
2025-12-28 15:49:43 +01:00

README.md

Verilator Simulation

Verilator is much faster than ModelSim but is restricted to Verilog/SystemVerilog. VHDL source code must be converted first.

Please use the convert scripts in case the VHDL code was changed. To be safe, a conversion is already part of the repo.

Prerequisites

You need CD images to use with the simulation. Only the .bin files are required. .chd is not supported.

Usage

./sim_top.sh
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