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db44bc7304
- Display file reader now avoids writing bitmap data into the pipeline during a blank phase - Fixes graphical corruption during fade transition in "Lost Eden" (noticable in first area when going forward and then back)
Verilator Simulation
Verilator is much faster than ModelSim but is restricted to Verilog/SystemVerilog. VHDL source code must be converted first.
Please use the convert scripts in case the VHDL code was changed. To be safe, a conversion is already part of the repo.
Prerequisites
You need CD images to use with the simulation. Only the .bin files are required. .chd is not supported.
Usage
./sim_top.sh