mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
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255 lines
5.8 KiB
NASM
255 lines
5.8 KiB
NASM
section .text
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org $400000
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vector:
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dc.l $1234
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dc.l main
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main:
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move.w #$0000,$303FFE ; Data buffer
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move.w #$2000,$E040C0 ; FMV SYSCMD - Decoder off
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nop
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move.w #$0100,$E040C0 ; FMV SYSCMD - Clear FIFO
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nop
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move.w #$1000,$E040C0 ; FMV SYSCMD - Decoder on
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move.w #$02D4,$E040DC ; FMV IVEC
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move.w #$F7CF,$E04060 ; FMV IER
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move.l #fmvirq,$168
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move.w #$807B,$E0300C ; FMA IVEC
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move.w #$013C,$E0301C ; FMA IER
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move.l #fmairq,$1EC
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move.w #$2480,$303FFC ; CDIC IVEC
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move.l #cdicirq,$200
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move #$2000,SR
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move.w #$0024,$303C00 ; Command Register = Reset Mode 2
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move.w #$8000,$303FFE ; Data buffer
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; #$01274700 Dragon's Lair Intro
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; #$00323400 FMVtest
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; #$00397400 7th Guest Philips Logo
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; #$55387000 7th Guest ?
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; #$01341100 Space Ace Intro
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; #$02140600 Space Ace Intro - Nearly the end (15 frames left)
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; #$00425900 2 Unlimited – Beyond Limits (Channel 0001)
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; #$42252600 Burger King - Multilanguage?
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; #$00152100 VideoCD Example (Channel ffff)
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; #$01164500 Coneheads (USA)
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; #$01414300 Coneheads (USA) Continue
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move.w #$002a,$303C00 ; Read Mode 2
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move.w #$0100,$303C06 ; File Register
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move.l #$ffffffff,$303C08 ; Channel Register
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move.w #$0000,$303C0C ; Audio Channel Register
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move.l #$01164500,$303C02 ; Timer Register
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move.w #$C000,$303FFE ; Start the Read by setting bit 15 of the data buffer
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jsr WaitForSectorAndUse
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jsr WaitForSectorAndUse
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lea timecodes,a2
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seek_forward:
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; We assume that the sequence header was decoded by now
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; Now stop the playback and continue at a different position
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move.w #$0000,$303FFE ; Stop reading from disc
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move.l (a2)+,$303C02 ; Timer Register
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move.w #$C000,$303FFE ; Start the Read by setting bit 15 of the data buffer
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move.w #$0100,$E040C0 ; FMV SYSCMD - Clear FIFO
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move.b #'Z',$80002019
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; Search for one picture to show
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waitforpics:
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jsr WaitForSectorAndUse
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cmp.w #1,$00E040A4
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bmi waitforpics
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move.b #'B',$80002019
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; And repeat ...
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bra seek_forward
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timecodes:
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dc.l $02050000
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dc.l $03000000
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dc.l $03050000
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dc.l $04000000
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dc.l $04050000
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dc.l $05000000
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dc.l $05050000
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dc.l $06000000
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dc.l $06050000
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dc.l $07000000
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dc.l $07050000
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dc.l $08000000
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dc.l $08050000
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dc.l $09000000
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dc.l $09050000
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dc.l $10000000
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dc.l $10050000
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dc.l $11000000
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dc.l $11050000
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dc.l $12000000
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dc.l $12050000
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dc.l $13000000
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dc.l $13050000
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dc.l $14000000
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dc.l $14050000
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dc.l $15000000
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dc.l $15050000
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dc.l $16000000
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dc.l $16050000
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dc.l $17000000
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dc.l $17050000
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dc.l $18000000
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dc.l $18050000
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dc.l $19000000
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dc.l $19050000
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dc.l $20000000
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dc.l $20050000
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dc.l $21000000
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dc.l $21050000
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dc.l $22000000
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dc.l $22050000
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dc.l $23000000
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dc.l $23050000
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dc.l $24000000
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dc.l $24050000
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dc.l $25000000
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dc.l $25050000
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dc.l $26000000
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dc.l $26050000
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dc.l $27000000
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dc.l $27050000
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dc.l $28000000
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dc.l $28050000
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dc.l $29000000
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dc.l $29050000
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WaitForSectorAndUse:
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jsr waitforcdicirq
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; We need to check for the Mode 2 header now. It can be either MPEG Audio or MPEG Video
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; MPEG Video should have submode 0x62 (Real Time Sector, Form and Video)
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; followed by a coding of 0x0f (for MPEG Video)
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; MPEG Audio should have 0x64 (Real Time Sector, Form and Video)
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; followed by a coding of 0x7f (for MPEG Audio)
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move.b 10(a0),d2
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cmp.b #$64,d2
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beq audio
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cmp.b #$62,d2
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beq video
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rts
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audio:
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; DMA CDIC to Memory
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move.b d0,$80004000 ; reset status
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move.l #$3000,$8000400c ; Memory Address Counter
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move.w #$480,$8000400a ; Size for MPEG Audio
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move.b #$92,$80004005 ; Dev. to Mem., 16 Bit Words,
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move.b #$80,$80004007 ; start DMA
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move.w d1,$303FF8 ; DMA Control Register = Start Transmission at a00
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; DMA Memory to FMA
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move.b d0,$80004040 ; reset status
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move.l #$3000,$8000404c ; Memory Address Counter
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move.w #$480,$8000404a ; Memory Transfer Counter
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move.b #$04,$80004046 ; SCR, MAC Count Up, DAC No Change (like the CDIC on CH1)
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move.b #$12,$80004045 ; Dev. to Mem., 16 Bit Words,
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move.b #$30,$80004044 ; ACK/RDY device (like the CDIC on CH1)
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move.b #$80,$80004047 ; start DMA
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move.w #$8002,$00E03000 ; Syscmd = Start DMA
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; Continue loop
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rts
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video:
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; DMA CDIC to Memory
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move.b d0,$80004000 ; reset status
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move.l #$3000,$8000400c ; Memory Address Counter
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move.w #$48a,$8000400a ; Size for MPEG Video
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move.b #$92,$80004005 ; Dev. to Mem., 16 Bit Words,
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move.b #$80,$80004007 ; start DMA
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move.w d1,$303FF8 ; DMA Control Register = Start Transmission at a00
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; DMA Memory to FMV
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; The original driver uses 0x484 for memory transfer counter
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; since the first 6 words are transferred via CPU to XFER
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; We are doing the same
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move.w $3000,$0e040de
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move.w $3002,$0e040de
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move.w $3004,$0e040de
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move.w $3006,$0e040de
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move.w $3008,$0e040de
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move.w $300a,$0e040de
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move.b d0,$80004040 ; reset status
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move.l #$300c,$8000400c ; Memory Address Counter
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move.w #$484,$8000404a ; Memory Transfer Counter
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move.b #$04,$80004046 ; SCR, MAC Count Up, DAC No Change (like the CDIC on CH1)
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move.b #$12,$80004045 ; Dev. to Mem., 16 Bit Words,
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move.b #$30,$80004044 ; ACK/RDY device (like the CDIC on CH1)
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move.b #$80,$80004047 ; start DMA
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move.w #$8000,$00E040C0 ; Syscmd = Start DMA
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rts
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waitforcdicirq:
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move #0,d0
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waitforcdicirqloop:
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cmp #0,d0
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beq waitforcdicirqloop
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move.b #'O',$80002019
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rts
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cdicirq:
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move.b #'I',$80002019
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move.w $303FF4,d0 ; clear flags on ABUFD
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; ignore ABUF
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move.w $303FF6,d0 ; clear flags on XBUF
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btst.l #$f,d0
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beq noint
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move.w $303FFe,d0
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btst.l #$0,d0 ; check lowest bit of data buffer
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beq lower_buf
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higher_buf:
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move.w #$8a0c,d1 ; DMA Control for 0x0A0C
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move.l #$300a00,a0 ; Buffer location in CDIC memory
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bra read_data
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lower_buf:
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move.w #$800c,d1 ; DMA Control for 0x000C
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move.l #$300000,a0 ; Buffer location in CDIC memory
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read_data:
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; Highest bit is set
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move #1,d0
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rte
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noint:
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move #0,d0
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rte
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fmvirq:
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move.b #'V',$80002019
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move $00E04062,d7
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rte
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fmairq:
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move.b #'A',$80002019
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move $00E0301A,d7
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rte
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