mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-06-14 03:04:32 +00:00
594bae844e
- Decoupled SEQ event from GOP event. Now behaves like real VMPEG hardware - Fixes Lost Ride gameplay after vehicle charge intro - Fixes timing accuracy of temp ref and time code Measurable with mv_status()
69 lines
1.5 KiB
Systemverilog
69 lines
1.5 KiB
Systemverilog
`ifndef HEADER_UTIL
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`define HEADER_UTIL
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typedef struct {
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bit [28:0] y_adr;
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bit [28:0] u_adr;
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bit [28:0] v_adr;
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bit first_intra_frame_of_gop;
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bit first_intra_frame_of_seq;
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bit [10:0] width;
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bit [8:0] height;
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bit [7:0] tempref;
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bit [31:0] timecode;
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} planar_yuv_s;
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typedef struct packed {
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bit [7:0] factor_r2r;
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bit [7:0] factor_l2r;
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bit [7:0] factor_r2l;
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bit [7:0] factor_l2l;
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} linear_volume_s;
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function [31:0] ones_mask(bit [4:0] n);
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begin
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ones_mask = (32'h1 << n) - 1; // n ones at LSB
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end
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endfunction
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function [31:0] reverse_endian_32;
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input [31:0] data_in;
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begin
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reverse_endian_32 = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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end
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endfunction
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// https://vlsiverify.com/verilog/verilog-codes/binary-to-gray/
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module b2g_converter #(
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parameter WIDTH = 4
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) (
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input [WIDTH-1:0] binary,
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output [WIDTH-1:0] gray
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);
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genvar i;
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generate
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for (i = 0; i < WIDTH - 1; i++) begin : bits
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assign gray[i] = binary[i] ^ binary[i+1];
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end
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endgenerate
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assign gray[WIDTH-1] = binary[WIDTH-1];
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endmodule
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// from https://vlsiverify.com/verilog/verilog-codes/gray-to-binary/
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module g2b_converter #(
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parameter WIDTH = 4
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) (
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input [WIDTH-1:0] gray,
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output [WIDTH-1:0] binary
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);
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genvar i;
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generate
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for (i = 0; i < WIDTH; i++) begin : bits
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assign binary[i] = ^(gray >> i);
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end
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endgenerate
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endmodule
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`endif
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