mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-06-14 03:04:32 +00:00
2aee070bd7
Replaced memory arrays of video decoder with dual port RAM for FPGA usage Added planar YCbCr frame player to display decoded frames Added DDR3 interface for frame player and pixel worker Added DDR3 interface mux for multiple masters MCD212: Added EV bit usage to replace backdrop with external video Shows Dragon's Lair intro with artefacts on MiSTer because the worker currently cannot read from DDR3 For some reason, the EV bit is not working correctly
87 lines
1.7 KiB
Systemverilog
87 lines
1.7 KiB
Systemverilog
`ifndef BUS_SVH
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`define BUS_SVH
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interface bus68k (
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input clk
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);
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bit write_strobe;
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bit as;
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bit lds;
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bit uds;
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bit [15:0] data_out;
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bit [23:1] addr;
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bit bus_ack;
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bit [15:0] data_in;
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modport master(output write_strobe, as, lds, uds, data_out, addr, input bus_ack, data_in);
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modport slave(input write_strobe, as, lds, uds, data_out, addr, output bus_ack, data_in);
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endinterface
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interface pixelstream (
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input clk
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);
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bit write;
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bit strobe;
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bit [7:0] pixel;
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modport source(output write, pixel, input strobe);
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modport sink(input write, pixel, output strobe);
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endinterface
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interface bytestream ();
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bit write;
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bit [7:0] data;
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modport source(output write, data);
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modport sink(input write, data);
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endinterface
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interface parallelel_spi ();
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bit [7:0] miso;
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bit [7:0] mosi;
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bit write;
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modport master(output mosi, write, input miso);
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modport slave(input mosi, write, output miso);
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endinterface
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interface audiostream ();
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bit write;
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bit strobe;
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bit signed [15:0] sample;
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modport source(output write, sample, input strobe);
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modport sink(input write, sample, output strobe);
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endinterface
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interface ddr_if;
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bit acquire;
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bit [28:0] addr;
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bit [63:0] wdata;
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bit [63:0] rdata;
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bit read;
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bit write;
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bit [ 7:0] burstcnt;
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bit [ 7:0] byteenable;
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bit busy;
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bit rdata_ready;
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modport to_host(
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output addr, wdata, read, write, burstcnt, byteenable, acquire,
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input rdata, busy, rdata_ready
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);
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modport from_host(
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output rdata, busy, rdata_ready,
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input addr, wdata, read, write, burstcnt, byteenable, acquire
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);
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endinterface
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`endif
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