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https://github.com/MiSTer-devel/CDi_MiSTer.git
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ca4216f956
- Fixes wrong offset with "Les Guignols de l’Info" - Fixes graphical corruption with "Christmas Crisis" - Fixes "skewed image corruption" with MPEG video - Adds support for NIS video event due to update of sequence parameters - Fixes "Philips Logo Intro" with "Brain Dead 13" Dynamic behavior is probably not yet correct. - "Christmas Crisis" is stuttering in the bonus rides. It should be noted that "Brain Dead 13" is still not working after the company logo.
6.6 KiB
6.6 KiB
SCC68070
Typical IRQ Vectors of the CD-i
Address Source Driver IRQ line
0x00000168 FMV fmvdrv IN4 (shared)
0x000001EC FMA madriv IN4 (shared)
0x00000200 CDIC cdapdriv IN4 (shared)
0x00000068 SLAVE IN2
0x000000F4 MCD212 INT1
DMA
Usage in CDIC driver
After
[:cdic] ':maincpu' (00429C42): ram_r: 0a02 : 1602 & ffff
[:cdic] ':maincpu' (00429C5E): ram_r: 0a0a : 0900 & ffff
[:cdic] ':maincpu' (0042AA12): cdic_w: DMA Control Register = 8a0c & ffff
the SCC68070 DMA is configured
DMA Read ADDR:00 DATA:0000 LDS:0 UDS:1 Read status register
DMA Write ADDR:00 DATA:ffff LDS:0 UDS:1 Perform status reset. Data is ignored.
DMA Write ADDR:06 DATA:0027 LDS:1 UDS:1 Memory Address 0x0027c450
DMA Write ADDR:07 DATA:c450 LDS:1 UDS:1 Memory Address 0x0027c450
DMA Write ADDR:05 DATA:0400 LDS:1 UDS:1 Transfer Count 0x400 operands
DMA Write ADDR:02 DATA:9292 LDS:1 UDS:0 OCR 0x92, Device to memory, Word Operands
DMA Write ADDR:03 DATA:8080 LDS:1 UDS:0 CCR 0x80, Start operation
Write CDIC DMA Control Register 1ffc 8a0c
Afterwards
DMA Access 0 00 0
DMA Access 0 00 0
DMA Access 0 00 0
the CPU seems to wait for DMA to finish.
MAME doesn't use the DMA. It performs high level DMA emulation for that. But we have to do it real.
Usage in FMV driver
cdapdriv operates on 0x48a words when fetching data for fmv. fmvdrv uses 0x484 words. The first 6 words are instead manually written to the XFER register. These 6 words contain the MPEG pack header with timing information. Afterwards the rest is transferred using DMA.
Example: First the fetch to memory
@0042AA08(cdapdriv) DMA1 BURST DEV => $00D4EBDC [$048A]
@0042AA0E(cdapdriv) WR.W 00D4EBDC <= 0000 [S] Start of MPEG Pack header
@0042AA0E(cdapdriv) WR.W 00D4EBDE <= 01BA [S]
@0042AA0E(cdapdriv) WR.W 00D4EBE0 <= 2100 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBE2 <= 0755 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBE4 <= 2180 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBE6 <= 1B91 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBE8 <= 0000 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBEA <= 01E0 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBEC <= 0902 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBEE <= FF0F [S]
@0042AA0E(cdapdriv) WR.W 00D4EBF0 <= CCED [S]
@0042AA0E(cdapdriv) WR.W 00D4EBF2 <= 3DF1 [S]
@0042AA0E(cdapdriv) WR.W 00D4EBF4 <= 5FEE [S]
...
@0042AA0E(cdapdriv) WR.W 00D4F4E8 <= 2A8E [S]
@0042AA0E(cdapdriv) WR.W 00D4F4EA <= 5069 [S]
@0042AA0E(cdapdriv) WR.W 00D4F4EC <= 7D0E [S]
@0042AA0E(cdapdriv) WR.W 00D4F4EE <= A1A5 [S]
Then the transfer to FMV
@00E54582(fmvdrv) DMA1 BURST DEV <= $00D4EBE8 [$0484]
@00E54588(fmvdrv) RD.W 00D4EBE8 => 0000 [S] Note the 6 word offset
@00E54588(fmvdrv) RD.W 00D4EBEA => 01E0 [S]
@00E54588(fmvdrv) RD.W 00D4EBEC => 0902 [S]
@00E54588(fmvdrv) RD.W 00D4EBEE => FF0F [S]
@00E54588(fmvdrv) RD.W 00D4EBF0 => CCED [S]
@00E54588(fmvdrv) RD.W 00D4EBF2 => 3DF1 [S]
@00E54588(fmvdrv) RD.W 00D4EBF4 => 5FEE [S]
...
@00E54588(fmvdrv) RD.W 00D4F4E8 => 2A8E [S]
@00E54588(fmvdrv) RD.W 00D4F4EA => 5069 [S]
@00E54588(fmvdrv) RD.W 00D4F4EC => 7D0E [S]
@00E54588(fmvdrv) RD.W 00D4F4EE => A1A5 [S]
DMA Read CH:1 ADDR:00 DATA:8000 LDS:0 UDS:1
DMA Write CH:1 ADDR:00 DATA:ffff LDS:0 UDS:1
DMA Write CH:1 ADDR:06 DATA:00d3 LDS:1 UDS:1 Memory Address Counter = 0x0d389dc (is in DVC RAM1)
DMA Write CH:1 ADDR:07 DATA:89dc LDS:1 UDS:1 Memory Address Counter = 0x0d389dc (is in DVC RAM1)
DMA Write CH:1 ADDR:05 DATA:0484 LDS:1 UDS:1 Memory Transfer Counter = 0x0484
DMA Write CH:1 ADDR:03 DATA:0404 LDS:0 UDS:1 SCR, MAC Count Up, DAC No Change (like the CDIC on CH1)
DMA Write CH:1 ADDR:02 DATA:1212 LDS:1 UDS:0 OCR 0x12, Memory to device, word operands
DMA Write CH:1 ADDR:02 DATA:3030 LDS:0 UDS:1 DCR 0x30, ACK/RDY device (like the CDIC on CH1)
DMA Write CH:1 ADDR:03 DATA:8080 LDS:1 UDS:0 CCR 0x80, Start operation
DVC Write 702060 8000 1 1
DVC Write SYSCMD Register 2060 8000
DMA Read CH:1 ADDR:00 DATA:0800 LDS:0 UDS:1
DMA Read CH:1 ADDR:00 DATA:0800 LDS:0 UDS:1
DMA Read CH:1 ADDR:00 DATA:0800 LDS:0 UDS:1
DMA Read CH:1 ADDR:00 DATA:0800 LDS:0 UDS:1
Usage in FMA driver
cdapdriv operates on 0x480 words when operating for fma. madriv always operates on 0x480 (1152) words?
Example: First the fetch to memory
@0042AA08(cdapdriv) DMA1 BURST DEV => $00D632AC [$0480]
@0042AA0E(cdapdriv) WR.W 00D632AC <= 0000 [S] Start of MPEG Pack header
@0042AA0E(cdapdriv) WR.W 00D632AE <= 01BA [S]
@0042AA0E(cdapdriv) WR.W 00D632B0 <= 2100 [S]
@0042AA0E(cdapdriv) WR.W 00D632B2 <= 07EB [S]
...
@0042AA0E(cdapdriv) WR.W 00D63BA4 <= C913 [S]
@0042AA0E(cdapdriv) WR.W 00D63BA6 <= 425A [S]
@0042AA0E(cdapdriv) WR.W 00D63BA8 <= 6566 [S]
@0042AA0E(cdapdriv) WR.W 00D63BAA <= 9A21 [S]
Then the transfer to FMA
@00E50EAA(madriv) RD.W 00D632AC => 0000 [S]
@00E50EAA(madriv) RD.W 00D632AE => 01BA [S]
@00E50EAA(madriv) RD.W 00D632B0 => 2100 [S]
@00E50EAA(madriv) RD.W 00D632B2 => 07EB [S]
@00E50EAA(madriv) RD.W 00D632B4 => 2180 [S]
@00E50EAA(madriv) RD.W 00D632B6 => 1B91 [S]
...
@00E50EAA(madriv) RD.W 00D63BA4 => C913 [S]
@00E50EAA(madriv) RD.W 00D63BA6 => 425A [S]
@00E50EAA(madriv) RD.W 00D63BA8 => 6566 [S]
@00E50EAA(madriv) RD.W 00D63BAA => 9A21 [S]
So, the data is really equal. There is no change of the MPEG stream involved. The CD-i base machine is an MPEG Audio data shovel.
DMA Read CH:1 ADDR:00 DATA:8000 LDS:0 UDS:1
DMA Write CH:1 ADDR:00 DATA:ffff LDS:0 UDS:1
DMA Write CH:1 ADDR:06 DATA:00d6 LDS:1 UDS:1 Memory Address Counter = 0x0d632ac (is in DVC RAM1)
DMA Write CH:1 ADDR:07 DATA:32ac LDS:1 UDS:1 Memory Address Counter = 0x0d632ac (is in DVC RAM1)
DMA Write CH:1 ADDR:05 DATA:0480 LDS:1 UDS:1 Memory Transfer Counter = 0x0480
DMA Write CH:1 ADDR:03 DATA:0404 LDS:0 UDS:1 SCR, MAC Count Up, DAC No Change (like the CDIC on CH1)
DMA Write CH:1 ADDR:02 DATA:1212 LDS:1 UDS:0 OCR 0x12, Memory to device, word operands
DMA Write CH:1 ADDR:02 DATA:3838 LDS:0 UDS:1 DCR 0x38, ACK/RDY device (like the CDIC on CH1), Bit 4 is ignored
DMA Write CH:1 ADDR:03 DATA:8080 LDS:1 UDS:0 CCR 0x80, Start operation
DVC Read e03000 0002 1 1
DVC Write e03000 8002 1 1
FMA CMD 1800 8002
FMA PACK a1 37120
DMA Read CH:1 ADDR:00 DATA:8000 LDS:0 UDS:1
DMA Read CH:1 ADDR:00 DATA:8000 LDS:1 UDS:0
DMA Read CH:1 ADDR:00 DATA:8000 LDS:0 UDS:1
DMA Read CH:1 ADDR:06 DATA:00d6 LDS:1 UDS:1
DMA Read CH:1 ADDR:07 DATA:3bac LDS:1 UDS:1