Files
CDi_MiSTer/scripts/apply_codestyle.sh
Andre Zeps 74bff4c5ce Removed slave rom from FPGA bitstream
Added ioctl_download for slave rom
boot0.rom is expected to be the main cpu rom
boot1.rom is expected to be the slave rom
2024-08-18 20:02:33 +02:00

8 lines
205 B
Bash
Executable File

#!/bin/bash
# This script applys a common codestyle to all verilog files
cd "$(dirname "$0")/../rtl"
verible-verilog-format --inplace --indentation_spaces 4 \
../rtl/*.v ../rtl/*.sv ../*.v ../*.sv