mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-05-24 03:03:09 +00:00
d20230609b
- SDRAM controller added - fixed 6805 bus timing with clk enable signal - fixed 6805 latch warnings in quartus - added 6805 reset logic - added 6805 ram zeroing after reset - fixed synthesis and timing of CDIC memory - MCD212 cpu bridge interfaces with SDRAM - fixed NvRAM memory timing - fixed spurious sdram access in reset - removed fake display_active flag - added SDRAM refresh logic - added real UART to SCC68070 - switched simulation top level to real MiSTer core video is corrupted and needs fixes
110 lines
3.8 KiB
Verilog
110 lines
3.8 KiB
Verilog
// From https://github.com/sipeed/TangNano-9K-example/blob/main/uart/src/uart_rx.v
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// verilator lint_off WIDTHEXPAND
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module uart_rx #(
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parameter CLK_FRE = 50, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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) (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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output reg [7:0] rx_data, //received serial data
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output reg rx_data_valid, //received serial data is valid
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input rx_data_ready, //data receiver module ready
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input rx_pin //serial data input
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);
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//calculates the clock cycle for baud rate
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg [ 2:0] state;
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reg [ 2:0] next_state;
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reg rx_d0; //delay 1 clock for rx_pin
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
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reg [ 7:0] rx_bits; //temporary storage of received data
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reg [15:0] cycle_cnt; //baud counter
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reg [ 2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0;
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end else begin
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rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) state <= S_IDLE;
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else state <= next_state;
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end
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always @(*) begin
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case (state)
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S_IDLE:
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if (rx_negedge) next_state = S_START;
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else next_state = S_IDLE;
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S_START:
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if (cycle_cnt == CYCLE - 1) //one data cycle
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next_state = S_REC_BYTE;
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else next_state = S_START;
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S_REC_BYTE:
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if (cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
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next_state = S_STOP;
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else next_state = S_REC_BYTE;
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S_STOP:
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if (cycle_cnt == CYCLE / 2 - 1) //half bit cycle,to avoid missing the next byte receiver
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next_state = S_DATA;
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else next_state = S_STOP;
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S_DATA:
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if (rx_data_ready) //data receive complete
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next_state = S_IDLE;
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else next_state = S_DATA;
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default: next_state = S_IDLE;
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endcase
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end
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) rx_data_valid <= 1'b0;
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else if (state == S_STOP && next_state != state) rx_data_valid <= 1'b1;
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else if (state == S_DATA && rx_data_ready) rx_data_valid <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) rx_data <= 8'd0;
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else if (state == S_STOP && next_state != state) rx_data <= rx_bits; //latch received data
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end
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) begin
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bit_cnt <= 3'd0;
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end else if (state == S_REC_BYTE)
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if (cycle_cnt == CYCLE - 1) bit_cnt <= bit_cnt + 3'd1;
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else bit_cnt <= bit_cnt;
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else bit_cnt <= 3'd0;
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end
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) cycle_cnt <= 16'd0;
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else if ((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else cycle_cnt <= cycle_cnt + 16'd1;
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end
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//receive serial data bit data
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) rx_bits <= 8'd0;
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else if (state == S_REC_BYTE && cycle_cnt == CYCLE / 2 - 1) rx_bits[bit_cnt] <= rx_pin;
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else rx_bits <= rx_bits;
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end
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endmodule
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