mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-05-31 03:03:53 +00:00
91450d6ca5
- Added clock divider to get 0.5 MHz from 30 MHz system clock The system timer tick now occurs every 8.1ms like it does on a 210/05 - Added reset delay mechanism to fix the resulting time out when polling for the PAL/NTSC status. This occurs when the m68k is overclocked - Added captured RC5 test data to confirm compatibility with the Thumbstick remote controller in a simulated environment
23 lines
475 B
Systemverilog
23 lines
475 B
Systemverilog
module resetdelay (
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input clk,
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input reset,
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input vsync, // Used to reduce the number of bits to count
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output bit delayedreset
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);
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bit [2:0] cnt;
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bit vsync_q;
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always_ff @(posedge clk) begin
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vsync_q <= vsync;
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if (reset) begin
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cnt <= 0;
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delayedreset <= 1;
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end else if (vsync && !vsync_q) begin
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cnt <= cnt + 1;
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if (cnt == '1) delayedreset <= 0;
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end
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end
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endmodule
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