- MPEG video decoder based on pl_mpeg, executed
on 3 VexiiRiscv cores. One for decoding the stream and
two for pixel workings and IDCT.
- Added additional clock for MPEG workers
- Added hardware accelerated DCT coefficient huffman decoder
- Generalized MPEG demuxer design for video and audio
- Removed fake startcode decoder for video stream (for now)
- Expanded Verilator testbench with YUV to RGB conversion
to extract decoded MPEG frames
- Dragon's Lair Intro can be decoded with this (vmpeg.asm)
Design cannot be synthesized
- Changes based on findings of the CDIC_BlackBoxAnalyzer project
- Removed side channel for audio coding
- A real CDIC reads the audio coding always from RAM
- Removed the concept of the audio tick found in MAME
- A real CDIC performs audio playback asynchronous to the CD reading
- Seek time now 19 sectors
- Fixes audio glitch in "Help cutscene" in "Zelda - Wand of Gamelon"
"Remember, tools can only be used..."
- Fixes audio regression during "Hotel Mario" score screen
- Fixed spurious IRQ caused by sector data interrupt after reading stopped
- Should fix hang on shopkeeper cutscene in "Zelda - Wand of Gamelon"
(Cannot be reproduced or is very unlikely now)
- Added state management for audiomap usage
- Added coding dependent sector playback delay
- Basic seeking time simulation and constant data rate
- Removed debugging option to disable MODE2 filters
- Added a lot documentation about expectations of
the CDIC to the code
- Splitted off all audio playback into seperate file
- Added DC bias filter to reduce pops between playbacks
- Fixed wrong sample during underflow of FIFO
- Added two sample delay for ADPCM
Fixes frequent clicks and pops due to latency of ADPCM calculation
- Buffer management now equal to CDIC emulation of MAME
Uses internal bank switching to avoid ADPCM overwrite
Stabilizes intro of "Zelda's Adventure" and "Hotel Mario"
SCC68070: DMA support for transfer to CDIC memory
Added additional test roms to verify the additions
Known issues:
- Hotel Mario hangs during score screen
- Frog Feast hangs ingame
- Added ICA1 and FILE1
- CLUT implemented as True Dual-Port RAM to allow
writing and reading with two video channels
- Added weight calculations
- Mouse cursor
- Attach display file and ICA to SDRAM
- Fixed byte order of 8 bit accesses by CPU
- Added SDRAM burst mode to fix video timing
- Fixed missing reset behavior of some components
- Added optional SDRAM zeroing
- Added SDRAM refresh during ROM download
- Added OS aware syscall parser to simulation
- Fixed SCC68070 on-chip interrupt autovector
- Fixed SCC68070 Timer0 frequency
- Added video pixel data FIFO
- Changed SDRAM auto refresh command
- SDRAM controller added
- fixed 6805 bus timing with clk enable signal
- fixed 6805 latch warnings in quartus
- added 6805 reset logic
- added 6805 ram zeroing after reset
- fixed synthesis and timing of CDIC memory
- MCD212 cpu bridge interfaces with SDRAM
- fixed NvRAM memory timing
- fixed spurious sdram access in reset
- removed fake display_active flag
- added SDRAM refresh logic
- added real UART to SCC68070
- switched simulation top level to real MiSTer core
video is corrupted and needs fixes
- CLUT7 RLE
- Video timing according to datasheet
- Example framebuffer in block ram
as SDRAM interface is not finished yet
- simulation can export video signal to PNG
- design can be synthesized and fitted but CPU parts are not functional
- SCC68070 is booting cdi200.rom
- SLAVE is communicating with the CPU
- MCD212 only implements memory map
- IRQs incomplete
- CDIC missing
- MiSTer interface missing
