- Display file reader now avoids writing bitmap data into the pipeline
during a blank phase
- Fixes graphical corruption during fade transition in "Lost Eden"
(noticable in first area when going forward and then back)
- Implement data reading state machine in CDIC
- Implement required interface to HPS for reading
cd sector data
- Add DMA support to CPU which is required
by the CDIC driver to get sector data into main
memory
- Add INT1 and INT2 to SCC68070
- Can boot into the demo of Frog Feast
- Servo HLE fixed to closed tray with
inserted CDi medium
- Add video IRQ
- Added servo controller SPI fake communication
Behaves as a closed but empty tray
- Added pointing device emulation
MiSTer joystick data used as input
Behaves like a maneuvering device
- Added SCI IRQ to 6805 cpu core
- Added SPI and SCI to 6805 uC
- Fixed spurious 68k chip select for slave
- Added documentation about I2C to the Front LCD
- Simulated U3090MG no longer causes front panel button presses
Lead to spurious IRQs before
- Removal of slave memory patches
- Attach display file and ICA to SDRAM
- Fixed byte order of 8 bit accesses by CPU
- Added SDRAM burst mode to fix video timing
- Fixed missing reset behavior of some components
- Added optional SDRAM zeroing
- Added SDRAM refresh during ROM download
- Added OS aware syscall parser to simulation
- Fixed SCC68070 on-chip interrupt autovector
- Fixed SCC68070 Timer0 frequency
- Added video pixel data FIFO
- Changed SDRAM auto refresh command
- SDRAM controller added
- fixed 6805 bus timing with clk enable signal
- fixed 6805 latch warnings in quartus
- added 6805 reset logic
- added 6805 ram zeroing after reset
- fixed synthesis and timing of CDIC memory
- MCD212 cpu bridge interfaces with SDRAM
- fixed NvRAM memory timing
- fixed spurious sdram access in reset
- removed fake display_active flag
- added SDRAM refresh logic
- added real UART to SCC68070
- switched simulation top level to real MiSTer core
video is corrupted and needs fixes
- CLUT7 RLE
- Video timing according to datasheet
- Example framebuffer in block ram
as SDRAM interface is not finished yet
- simulation can export video signal to PNG
- design can be synthesized and fitted but CPU parts are not functional
- SCC68070 is booting cdi200.rom
- SLAVE is communicating with the CPU
- MCD212 only implements memory map
- IRQs incomplete
- CDIC missing
- MiSTer interface missing
