- SDRAM controller added
- fixed 6805 bus timing with clk enable signal
- fixed 6805 latch warnings in quartus
- added 6805 reset logic
- added 6805 ram zeroing after reset
- fixed synthesis and timing of CDIC memory
- MCD212 cpu bridge interfaces with SDRAM
- fixed NvRAM memory timing
- fixed spurious sdram access in reset
- removed fake display_active flag
- added SDRAM refresh logic
- added real UART to SCC68070
- switched simulation top level to real MiSTer core
video is corrupted and needs fixes
