From db44bc73042acaa2b0ab74f7fdddca3fd83716ff Mon Sep 17 00:00:00 2001 From: Andre Zeps Date: Sat, 22 Nov 2025 12:52:36 +0100 Subject: [PATCH] MCD212: Fixed switch from CLUT to DYUV without VSR reload - Display file reader now avoids writing bitmap data into the pipeline during a blank phase - Fixes graphical corruption during fade transition in "Lost Eden" (noticable in first area when going forward and then back) --- README.md | 1 - files.qip | 2 +- ...file_decoder.sv => display_file_reader.sv} | 13 +++++++-- rtl/mcd212.sv | 11 +++++--- sim/fx68.mpf | 2 +- sim2/videosim.sh | 1 + sim2/videosim_top.cpp | 27 ++----------------- 7 files changed, 24 insertions(+), 33 deletions(-) rename rtl/{display_file_decoder.sv => display_file_reader.sv} (92%) diff --git a/README.md b/README.md index 6c7762f..1a832da 100644 --- a/README.md +++ b/README.md @@ -74,7 +74,6 @@ Expected synthesis times with Quartus 17.0.2 * "The Secret of Nimh" (Philips Edition) has the wrong frame rate? Sometimes? * "The Secret of Nimh" (VCD) doesn't play * Huffman decoding in state 14 takes too long -* Broken crossfade effect when moving without FMV in "Lost Eden" * Slow motion with VCDs is behaving incorrect * Leaving the cake Puzzle in 7th Guest freezes (everytime?) * Weird shifted graphics with "David and Goliath" diff --git a/files.qip b/files.qip index d439a22..13ffff7 100644 --- a/files.qip +++ b/files.qip @@ -9,7 +9,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/cditop.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/clut_rle.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddr_mux3.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/delta_yuv_decoder.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/display_file_decoder.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/display_file_reader.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/dual_ad7528.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/flag_cross_domain.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/hps_cd_sector_cache.sv diff --git a/rtl/display_file_decoder.sv b/rtl/display_file_reader.sv similarity index 92% rename from rtl/display_file_decoder.sv rename to rtl/display_file_reader.sv index 09ecfa0..b5f814a 100644 --- a/rtl/display_file_decoder.sv +++ b/rtl/display_file_reader.sv @@ -3,9 +3,11 @@ //`define DEBUG `define dp(statement) `ifdef DEBUG $display``statement `endif -module display_file_decoder ( +module display_file_reader ( input clk, input reset, + input st, + input hsync, output bit [21:0] address, output bit as, input [15:0] din, @@ -110,7 +112,14 @@ module display_file_decoder ( bit indizes_equal_during_write_d; bit indizes_equal_during_write_q; - assign out.write = count != 0 && !reset && !indizes_equal_during_write_q; + bit [8:0] pixelcounter; + wire line_ended = pixelcounter >= (st ? 360 : 384); + always_ff @(posedge clk) begin + if (hsync) pixelcounter <= 0; + else if (out.write && out.strobe) pixelcounter <= pixelcounter + 1; + end + + assign out.write = count != 0 && !reset && !indizes_equal_during_write_q && !line_ended; always_comb begin read_index_d = read_index_q; diff --git a/rtl/mcd212.sv b/rtl/mcd212.sv index cfb9d5e..c31d740 100644 --- a/rtl/mcd212.sv +++ b/rtl/mcd212.sv @@ -725,11 +725,13 @@ module mcd212 ( pixelstream file0_out (.clk); // Plane A Display File Decoder - display_file_decoder #( + display_file_reader #( .unit_index(0) ) file0 ( .clk, .reset(new_frame || reset || !command_register_dcr1.ic1), + .st(control_register_crsr1w.st), + .hsync(hsync), .address(file0_adr), .as(file0_as), .din(file0_din), @@ -744,11 +746,13 @@ module mcd212 ( pixelstream file1_out (.clk); - display_file_decoder #( + display_file_reader #( .unit_index(1) ) file1 ( .clk, .reset(new_frame || reset || !command_register_dcr2.ic2), + .st(control_register_crsr1w.st), + .hsync(hsync), .address(file1_adr), .as(file1_as), .din(file1_din), @@ -896,7 +900,8 @@ module mcd212 ( end always_ff @(posedge clk) begin - if (ica0_reload_vsr) `dp_vsr(("Reload VSR %x", ica0_vsr)); + if (ica0_reload_vsr) `dp_vsr(("Reload VSR0 %x", ica0_vsr)); + if (ica1_reload_vsr) `dp_vsr(("Reload VSR1 %x", ica1_vsr)); if (dca0_read) `dp_dcaptr(("Start DCA0 on line %d", video_y)); if (dca1_read) `dp_dcaptr(("Start DCA1 on line %d", video_y)); diff --git a/sim/fx68.mpf b/sim/fx68.mpf index 7fffcf0..fc92b20 100644 --- a/sim/fx68.mpf +++ b/sim/fx68.mpf @@ -417,7 +417,7 @@ Project_File_0 = /home/andre/GIT/scc68070/rtl/ica_dca_ctrl.sv Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1723915689 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = /home/andre/GIT/scc68070/tg68k/TG68KdotC_Kernel.vhd Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1723490422 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_2 = /home/andre/GIT/scc68070/rtl/display_file_decoder.sv +Project_File_2 = /home/andre/GIT/scc68070/rtl/display_file_reader.sv Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1723913713 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_3 = /home/andre/GIT/scc68070/rtl/videofifo.sv Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1723911345 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 diff --git a/sim2/videosim.sh b/sim2/videosim.sh index e991e5a..f10e9d9 100755 --- a/sim2/videosim.sh +++ b/sim2/videosim.sh @@ -1,3 +1,4 @@ +mkdir -p videosim verilator --top-module emu \ --trace --trace-fst --trace-structs --cc --assert --exe --build \ --build-jobs 8 videosim_top.cpp -I../rtl \ diff --git a/sim2/videosim_top.cpp b/sim2/videosim_top.cpp index 5acb8d1..afce66f 100644 --- a/sim2/videosim_top.cpp +++ b/sim2/videosim_top.cpp @@ -356,32 +356,8 @@ class CDi { } #endif - // Simulate CD data delivery from HPS + // Ignore CD data delivery from HPS if (dut.rootp->emu__DOT__cd_hps_req && sd_rd_q == 0 && dut.rootp->emu__DOT__nvram_hps_ack == 0) { - assert(dut.rootp->emu__DOT__cd_hps_ack == 0); - dut.rootp->emu__DOT__cd_hps_ack = 1; - - uint32_t lba = dut.rootp->emu__DOT__cd_hps_lba; - uint32_t m_time = dut.rootp->emu__DOT__cditop__DOT__cdic_inst__DOT__time_register; - - uint32_t reference_lba = lba_from_time(m_time); - // assert(lba == reference_lba); - // assert(lba >= 150); - - if (lba < 150) - lba += 150; - uint32_t file_offset = (lba - 150) * kSectorSize; - - printf("Request CD Sector %x %x %x\n", m_time, lba, file_offset); - - int res = fseek(f_cd_bin, file_offset, SEEK_SET); - assert(res == 0); - - fread(hps_buffer, 1, kSectorSize, f_cd_bin); - - struct subcode &out = *reinterpret_cast(&hps_buffer[kSectorSize / 2]); - subcode_data(dut.rootp->emu__DOT__cd_hps_lba, out); - hps_buffer_index = 0; } if (dut.rootp->emu__DOT__nvram_hps_rd && sd_rd_q == 0 && dut.rootp->emu__DOT__cd_hps_ack == 0) { @@ -562,6 +538,7 @@ class CDi { dut.trace(&m_trace, 5); if (do_trace) { + char filename[100]; sprintf(filename, "/tmp/waveform.vcd", instanceid); fprintf(stderr, "Writing to %s\n", filename); m_trace.open(filename);