From 83a2ed43aa2fd600a02c405f27bd7f7275b34ea3 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sun, 25 Aug 2019 08:44:32 +0800 Subject: [PATCH] Support for Direct Video. --- c64.sv | 31 +++++++--- sys/hdmi_config.sv | 58 +++++++++---------- sys/hps_io.v | 8 ++- sys/pll.qip | 68 +++++++++++----------- sys/pll.v | 14 +++-- sys/pll/pll_0002.v | 39 +++++++------ sys/sys_top.sdc | 7 ++- sys/sys_top.v | 138 +++++++++++++++++++++++++++++++-------------- video_sync.vhd | 18 +++--- 9 files changed, 229 insertions(+), 152 deletions(-) diff --git a/c64.sv b/c64.sv index 457b9dc..078cb05 100644 --- a/c64.sv +++ b/c64.sv @@ -177,12 +177,14 @@ localparam CONF_STR = { wire pll_locked; wire clk_sys; wire clk64; +wire clk96; pll pll ( .refclk(CLK_50M), - .outclk_0(clk64), - .outclk_1(clk_sys), + .outclk_0(clk96), + .outclk_1(clk64), + .outclk_2(clk_sys), .reconfig_to_pll(reconfig_to_pll), .reconfig_from_pll(reconfig_from_pll), .locked(pll_locked) @@ -231,14 +233,16 @@ always @(posedge CLK_50M) begin cfg_data <= 0; cfg_write <= 1; end + /* 3: begin cfg_address <= 4; cfg_data <= ntsc_r ? 'h20504 : 'h404; cfg_write <= 1; end + */ 5: begin cfg_address <= 7; - cfg_data <= ntsc_r ? 702807747 : 3555492125; + cfg_data <= ntsc_r ? 3357876127 : 1503512573; cfg_write <= 1; end 7: begin @@ -866,13 +870,24 @@ always @(posedge clk_sys) begin end end -reg [3:0] clkdivpix; -always @(posedge clk64) clkdivpix <= clkdivpix + 1'b1; +reg ce_pix; +always @(posedge clk96) begin + reg [3:0] div; + reg lores; + + div <= div + 1'b1; + + if(div == 11) begin + div <= 0; + lores <= ~lores; + end + + ce_pix <= (~lores | ~hq2x160) && !div; +end -wire ce_pix = (~clkdivpix[3] | ~hq2x160) & ~clkdivpix[2] & ~clkdivpix[1] & ~clkdivpix[0]; wire scandoubler = status[10:8] || forced_scandoubler; -assign CLK_VIDEO = clk64; +assign CLK_VIDEO = clk96; assign VIDEO_ARX = status[5:4] ? 8'd16 : 8'd4; assign VIDEO_ARY = status[5:4] ? 8'd9 : 8'd3; assign VGA_SL = (status[10:8] > 2) ? status[9:8] - 2'd2 : 2'd0; @@ -880,7 +895,7 @@ assign VGA_F1 = 0; video_mixer video_mixer ( - .clk_sys(clk64), + .clk_sys(clk96), .ce_pix(ce_pix), .ce_pix_out(CE_PIXEL), diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv index 8cbad8b..ada954f 100644 --- a/sys/hdmi_config.sv +++ b/sys/hdmi_config.sv @@ -2,12 +2,14 @@ module hdmi_config ( // Host Side - input iCLK, - input iRST_N, + input iCLK, + input iRST_N, input dvi_mode, input audio_96k, - input hdmi_limited, + input limited, + input ypbpr, + output reg done, // I2C Side @@ -105,34 +107,32 @@ wire [15:0] init_data[82] = {8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0 - {8'h18, hdmi_limited, // CSC enable [7]. 0 - Off. 1 - On. - 7'h0D}, // CSC Scaling Factors and Coefficients for RGB Full->Limited. - {8'h19, 8'hBC}, // Taken from table in ADV7513 Programming Guide. - {8'h1A, 8'h00}, // CSC Channel A. - {8'h1B, 8'h00}, - {8'h1C, 8'h00}, - {8'h1D, 8'h00}, - {8'h1E, 8'h01}, + {8'h18, ypbpr ? 8'h88 : limited ? 8'h8D : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited. + {8'h19, ypbpr ? 8'h2E : 8'hBC}, // Taken from table in ADV7513 Programming Guide. + {8'h1A, ypbpr ? 8'h18 : 8'h00}, // CSC Channel A. + {8'h1B, ypbpr ? 8'h93 : 8'h00}, + {8'h1C, ypbpr ? 8'h1F : 8'h00}, + {8'h1D, ypbpr ? 8'h3F : 8'h00}, + {8'h1E, ypbpr ? 8'h08 : 8'h01}, {8'h1F, 8'h00}, - - {8'h20, 8'h00}, // CSC Channel B. - {8'h21, 8'h00}, - {8'h22, 8'h0D}, - {8'h23, 8'hBC}, - {8'h24, 8'h00}, - {8'h25, 8'h00}, - {8'h26, 8'h01}, + + {8'h20, ypbpr ? 8'h03 : 8'h00}, // CSC Channel B. + {8'h21, ypbpr ? 8'h67 : 8'h00}, + {8'h22, ypbpr ? 8'h0B : 8'h0D}, + {8'h23, ypbpr ? 8'h71 : 8'hBC}, + {8'h24, ypbpr ? 8'h01 : 8'h00}, + {8'h25, ypbpr ? 8'h28 : 8'h00}, + {8'h26, ypbpr ? 8'h00 : 8'h01}, {8'h27, 8'h00}, - - {8'h28, 8'h00}, // CSC Channel C. - {8'h29, 8'h00}, - {8'h2A, 8'h00}, - {8'h2B, 8'h00}, - {8'h2C, 8'h0D}, - {8'h2D, 8'hBC}, - {8'h2E, 8'h01}, + + {8'h28, ypbpr ? 8'h1E : 8'h00}, // CSC Channel C. + {8'h29, ypbpr ? 8'h21 : 8'h00}, + {8'h2A, ypbpr ? 8'h19 : 8'h00}, + {8'h2B, ypbpr ? 8'hB2 : 8'h00}, + {8'h2C, ypbpr ? 8'h08 : 8'h0D}, + {8'h2D, ypbpr ? 8'h2D : 8'hBC}, + {8'h2E, ypbpr ? 8'h08 : 8'h01}, {8'h2F, 8'h00}, - {8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx. @@ -152,7 +152,7 @@ wire [15:0] init_data[82] = {8'h57, 1'b0, // [7] IT Content. 0 - No. 1 - Yes (type set in register h59). 3'b000, // [6:4] Color space (ignored for RGB) - hdmi_limited ? 2'b01 : 2'b10, // [3:2] RGB Quantization range + (ypbpr | limited) ? 2'b01 : 2'b10, // [3:2] RGB Quantization range 2'b00}, // [1:0] Non-Uniform Scaled: 00 - None. 01 - Horiz. 10 - Vert. 11 - Both. 16'h7301, diff --git a/sys/hps_io.v b/sys/hps_io.v index 013ac75..cc75f12 100644 --- a/sys/hps_io.v +++ b/sys/hps_io.v @@ -83,12 +83,13 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) output reg [DW:0] sd_buff_dout, input [DW:0] sd_buff_din, output reg sd_buff_wr, + input [15:0] sd_req_type, // ARM -> FPGA download output reg ioctl_download = 0, // signal indicating an active download output reg [7:0] ioctl_index, // menu index used to upload the file output reg ioctl_wr, - output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2 + output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2 output reg [DW:0] ioctl_dout, output reg [31:0] ioctl_file_ext, input ioctl_wait, @@ -199,7 +200,7 @@ always @(posedge clk_vid) begin if(old_vs & ~vs) begin vid_int <= {vid_int[0],f1}; - if(~f1) begin + if(~f1) begin if(hcnt && vcnt) begin old_vmode <= new_vmode; @@ -390,6 +391,7 @@ always@(posedge clk_sys) begin 1: io_dout <= sd_cmd; 2: io_dout <= sd_lba[15:0]; 3: io_dout <= sd_lba[31:16]; + 4: io_dout <= sd_req_type; endcase // send SD config IO -> FPGA @@ -571,7 +573,7 @@ always@(posedge clk_sys) begin reg [15:0] cmd; reg [2:0] cnt; reg has_cmd; - reg [24:0] addr; + reg [26:0] addr; reg wr; ioctl_wr <= wr; diff --git a/sys/pll.qip b/sys/pll.qip index ea5b683..90cd16e 100644 --- a/sys/pll.qip +++ b/sys/pll.qip @@ -37,17 +37,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::dHJ1ZQ==::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::OA==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MzU1NTQ5MjEyNQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MTE=::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MTUwMzUxMjU3Mw==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NjMuMDU1OTEx::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::Nw==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzU1NTQ5MjEyNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::Ng==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTE=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUwMzUxMjU3Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" @@ -56,10 +56,10 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjMuMDU1OTEx::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MTQ=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MzU1NTQ5MjEyNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::OQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTE=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTUwMzUxMjU3Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::OQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" @@ -68,10 +68,10 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MzEuNTI3OTU2::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MjA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MjYyNTAwNjcwMg==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MTg=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTE=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTUwMzUxMjU3Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTg=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" @@ -258,13 +258,13 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NjMuMDU1OTEwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::OTQuNTgzODY1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MzEuNTI3OTU1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NjMuMDU1OTEwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MzEuNTI3OTU1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" @@ -319,34 +319,34 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::Ng==::bV9jbnRfaGlfZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NQ==::bV9jbnRfbG9fZGl2" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::dHJ1ZQ==::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::NA==::Y19jbnRfaGlfZGl2MA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mw==::Y19jbnRfaGlfZGl2MA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::Mw==::Y19jbnRfbG9fZGl2MA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::Nw==::Y19jbnRfaGlfZGl2MQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::Nw==::Y19jbnRfbG9fZGl2MQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::NQ==::Y19jbnRfaGlfZGl2MQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::NA==::Y19jbnRfbG9fZGl2MQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::OQ==::Y19jbnRfaGlfZGl2Mg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::OQ==::Y19jbnRfbG9fZGl2Mg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw==" @@ -456,15 +456,15 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MzA=::cGxsX2NwX2N1cnJlbnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::MjAwMA==::cGxsX2J3Y3RybA==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQxLjM5MTM3IE1Ieg==::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzU1NTQ5MjEyNQ==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NTY3LjUwMzE5IE1Ieg==::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MTUwMzUxMjU3Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw3LDcsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwzMCwyMDAwLDQ0MS4zOTEzNyBNSHosMzU1NTQ5MjEyNSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDMsMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1LDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw5LDksMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwzMCwyMDAwLDU2Ny41MDMxOSBNSHosMTUwMzUxMjU3Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" diff --git a/sys/pll.v b/sys/pll.v index 6ec4b78..3a2d896 100644 --- a/sys/pll.v +++ b/sys/pll.v @@ -10,6 +10,7 @@ module pll ( input wire rst, // reset.reset output wire outclk_0, // outclk0.clk output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk output wire locked, // locked.export input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll @@ -20,6 +21,7 @@ module pll ( .rst (rst), // reset.reset .outclk_0 (outclk_0), // outclk0.clk .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk .locked (locked), // locked.export .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll .reconfig_from_pll (reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll @@ -67,13 +69,13 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -82,7 +84,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -91,7 +93,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v index dfb5f84..f588583 100644 --- a/sys/pll/pll_0002.v +++ b/sys/pll/pll_0002.v @@ -13,6 +13,9 @@ module pll_0002( // interface 'outclk1' output wire outclk_1, + // interface 'outclk2' + output wire outclk_2, + // interface 'locked' output wire locked, @@ -29,14 +32,14 @@ module pll_0002( .pll_fractional_cout(32), .pll_dsm_out_sel("1st_order"), .operation_mode("direct"), - .number_of_clocks(2), - .output_clock_frequency0("63.055910 MHz"), + .number_of_clocks(3), + .output_clock_frequency0("94.583865 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), - .output_clock_frequency1("31.527955 MHz"), + .output_clock_frequency1("63.055910 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), + .output_clock_frequency2("31.527955 MHz"), .phase_shift2("0 ps"), .duty_cycle2(50), .output_clock_frequency3("0 MHz"), @@ -86,34 +89,34 @@ module pll_0002( .duty_cycle17(50), .pll_type("Cyclone V"), .pll_subtype("Reconfigurable"), - .m_cnt_hi_div(4), - .m_cnt_lo_div(4), + .m_cnt_hi_div(6), + .m_cnt_lo_div(5), .n_cnt_hi_div(256), .n_cnt_lo_div(256), .m_cnt_bypass_en("false"), .n_cnt_bypass_en("true"), - .m_cnt_odd_div_duty_en("false"), + .m_cnt_odd_div_duty_en("true"), .n_cnt_odd_div_duty_en("false"), - .c_cnt_hi_div0(4), + .c_cnt_hi_div0(3), .c_cnt_lo_div0(3), .c_cnt_prst0(1), .c_cnt_ph_mux_prst0(0), .c_cnt_in_src0("ph_mux_clk"), .c_cnt_bypass_en0("false"), - .c_cnt_odd_div_duty_en0("true"), - .c_cnt_hi_div1(7), - .c_cnt_lo_div1(7), + .c_cnt_odd_div_duty_en0("false"), + .c_cnt_hi_div1(5), + .c_cnt_lo_div1(4), .c_cnt_prst1(1), .c_cnt_ph_mux_prst1(0), .c_cnt_in_src1("ph_mux_clk"), .c_cnt_bypass_en1("false"), - .c_cnt_odd_div_duty_en1("false"), - .c_cnt_hi_div2(1), - .c_cnt_lo_div2(1), + .c_cnt_odd_div_duty_en1("true"), + .c_cnt_hi_div2(9), + .c_cnt_lo_div2(9), .c_cnt_prst2(1), .c_cnt_ph_mux_prst2(0), .c_cnt_in_src2("ph_mux_clk"), - .c_cnt_bypass_en2("true"), + .c_cnt_bypass_en2("false"), .c_cnt_odd_div_duty_en2("false"), .c_cnt_hi_div3(1), .c_cnt_lo_div3(1), @@ -223,8 +226,8 @@ module pll_0002( .pll_vco_div(2), .pll_cp_current(30), .pll_bwctrl(2000), - .pll_output_clk_frequency("441.39137 MHz"), - .pll_fractional_division("3555492125"), + .pll_output_clk_frequency("567.50319 MHz"), + .pll_fractional_division("1503512573"), .mimic_fbclk_type("none"), .pll_fbclk_mux_1("glb"), .pll_fbclk_mux_2("m_cnt"), @@ -232,7 +235,7 @@ module pll_0002( .pll_slf_rst("true") ) altera_pll_i ( .rst (rst), - .outclk ({outclk_1, outclk_0}), + .outclk ({outclk_2, outclk_1, outclk_0}), .locked (locked), .reconfig_to_pll (reconfig_to_pll), .fboutclk ( ), diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index c253d88..922169c 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -3,7 +3,7 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] -create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_sck +create_clock -period 10.0ns [get_pins -compatibility_mode spi|sclk_out] -name spi_sck derive_pll_clocks @@ -20,8 +20,8 @@ set_clock_groups -asynchronous \ -group [get_clocks { *|h2f_user0_clk}] \ -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] -set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] -set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] +set_output_delay -max -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] +set_output_delay -min -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}] @@ -36,3 +36,4 @@ set_false_path -from * -to [get_ports {VGA_*}] set_false_path -from * -to [get_ports {AUDIO_SPDIF}] set_false_path -from * -to [get_ports {AUDIO_L}] set_false_path -from * -to [get_ports {AUDIO_R}] +set_false_path -from * -to [get_keepers {cfg[*]}] diff --git a/sys/sys_top.v b/sys/sys_top.v index 5d0a8bb..493bf34 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -257,12 +257,13 @@ reg cfg_set = 0; wire hdmi_limited = cfg[8]; wire dvi_mode = cfg[7]; wire audio_96k = cfg[6]; +wire direct_video = cfg[10]; +wire csync = cfg[3]; +wire ypbpr_en = cfg[5]; +wire io_osd_vga= io_ss1 & ~io_ss2; `ifndef DUAL_SDRAM wire sog = cfg[9]; - wire ypbpr_en = cfg[5]; - wire csync = cfg[3]; wire vga_scaler= cfg[2]; - wire io_osd_vga= io_ss1 & ~io_ss2; `endif reg cfg_custom_t = 0; @@ -431,7 +432,7 @@ always @(posedge FPGA_CLK2_50) begin end wire clk_100m; -wire clk_hdmi = ~HDMI_TX_CLK; // Internal HDMI clock, inverted in relation to external clock +wire clk_hdmi = hdmi_tx_clk; wire clk_audio = FPGA_CLK3_50; wire clk_pal = FPGA_CLK3_50; @@ -496,6 +497,7 @@ wire [127:0] vbuf_writedata; wire [15:0] vbuf_byteenable; wire vbuf_write; +wire hdmi_vs, hdmi_hs; ascal #( .RAMBASE(32'h20000000), @@ -528,8 +530,8 @@ ascal .o_r (hdmi_data[23:16]), .o_g (hdmi_data[15:8]), .o_b (hdmi_data[7:0]), - .o_hs (HDMI_TX_HS), - .o_vs (HDMI_TX_VS), + .o_hs (hdmi_hs), + .o_vs (hdmi_vs), .o_de (hdmi_de), .o_lltune (lltune), .htotal (WIDTH + HFP + HBP + HS), @@ -687,13 +689,14 @@ fbpal fbpal ///////////////////////// HDMI output ///////////////////////////////// +wire hdmi_tx_clk; pll_hdmi pll_hdmi ( .refclk(FPGA_CLK1_50), .rst(reset_req), .reconfig_to_pll(reconfig_to_pll), .reconfig_from_pll(reconfig_from_pll), - .outclk_0(HDMI_TX_CLK) + .outclk_0(hdmi_tx_clk) ); //1920x1080@60 PCLK=148.5MHz CEA @@ -772,7 +775,8 @@ hdmi_config hdmi_config .dvi_mode(dvi_mode), .audio_96k(audio_96k), - .hdmi_limited(hdmi_limited) + .limited(hdmi_limited), + .ypbpr(ypbpr_en & direct_video) ); wire [23:0] hdmi_data; @@ -790,6 +794,8 @@ scanlines #(1) HDMI_scanlines .vs(HDMI_TX_VS) ); +wire [23:0] hdmi_tx_d; +wire hdmi_tx_de; osd hdmi_osd ( .clk_sys(clk_sys), @@ -800,56 +806,102 @@ osd hdmi_osd .clk_video(clk_hdmi), .din(hdmi_data_sl), - .dout(HDMI_TX_D), + .dout(hdmi_tx_d), .de_in(hdmi_de), - .de_out(HDMI_TX_DE), + .de_out(hdmi_tx_de), .osd_status(osd_status) ); +reg [23:0] dv_d; +reg dv_hs, dv_vs, dv_de; +always @(negedge clk_vid) begin + reg [23:0] dv_d1, dv_d2; + reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2; + reg [12:0] vsz, vcnt; + reg old_hs, old_vs; + reg vde; + reg [3:0] hss; + + if(ce_pix) begin + hss <= (hss << 1) | hs; + + old_hs <= hs; + if(~old_hs && hs) begin + old_vs <= vs; + if(~&vcnt) vcnt <= vcnt + 1'd1; + if(~old_vs & vs & ~f1) vsz <= vcnt; + if(old_vs & ~vs) vcnt <= 0; + + if(vcnt == 1) vde <= 1; + if(vcnt == vsz - 3) vde <= 0; + end + + dv_de1 <= !{hss,hs} && vde; + dv_hs1 <= csync ? (vs ^ hs) : hs; + dv_vs1 <= vs; + end + + dv_d1 <= vga_q; + dv_d2 <= dv_d1; + dv_de2 <= dv_de1; + dv_hs2 <= dv_hs1; + dv_vs2 <= dv_vs1; + + dv_d <= dv_d2; + dv_de <= dv_de2; + dv_hs <= dv_hs2; + dv_vs <= dv_vs2; +end + +assign HDMI_TX_CLK = direct_video ? clk_vid : hdmi_tx_clk; +assign HDMI_TX_HS = direct_video ? dv_hs : hdmi_hs ; +assign HDMI_TX_VS = direct_video ? dv_vs : hdmi_vs ; +assign HDMI_TX_D = direct_video ? dv_d : hdmi_tx_d ; +assign HDMI_TX_DE = direct_video ? dv_de : hdmi_tx_de ; + ///////////////////////// VGA output ////////////////////////////////// +wire [23:0] vga_data_sl; + +scanlines #(0) VGA_scanlines +( + .clk(clk_vid), + + .scanlines(scanlines), + .din(de ? {r_out, g_out, b_out} : 24'd0), + .dout(vga_data_sl), + .hs(hs), + .vs(vs) +); + +wire [23:0] vga_q; +osd vga_osd +( + .clk_sys(clk_sys), + + .io_osd(io_osd_vga), + .io_strobe(io_strobe), + .io_din(io_din), + + .clk_video(clk_vid), + .din(vga_data_sl), + .dout(vga_q), + .de_in(de) +); + `ifndef DUAL_SDRAM - wire [23:0] vga_data_sl; - - scanlines #(0) VGA_scanlines - ( - .clk(clk_vid), - - .scanlines(scanlines), - .din(de ? {r_out, g_out, b_out} : 24'd0), - .dout(vga_data_sl), - .hs(hs1), - .vs(vs1) - ); - - osd vga_osd - ( - .clk_sys(clk_sys), - - .io_osd(io_osd_vga), - .io_strobe(io_strobe), - .io_din(io_din), - - .clk_video(clk_vid), - .din(vga_data_sl), - .dout(vga_q), - .de_in(de) - ); - - wire [23:0] vga_q; wire [23:0] vga_o; - vga_out vga_out ( - .ypbpr_full(1), + .ypbpr_full(0), .ypbpr_en(ypbpr_en), .dout(vga_o), - .din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q) + .din(vga_scaler ? {24{hdmi_tx_de}} & hdmi_tx_d : vga_q) ); - wire vs1 = vga_scaler ? HDMI_TX_VS : vs; - wire hs1 = vga_scaler ? HDMI_TX_HS : hs; + wire vs1 = vga_scaler ? hdmi_vs : vs; + wire hs1 = vga_scaler ? hdmi_hs : hs; assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync ? 1'b1 : ~vs1; assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1; diff --git a/video_sync.vhd b/video_sync.vhd index ca64f8c..0fac83f 100644 --- a/video_sync.vhd +++ b/video_sync.vhd @@ -64,10 +64,11 @@ process(clk32) end if; if ntsc = '1' then - if dot_count = 010 then hsync_out <= '1'; end if; - if dot_count = 048 then hsync_out <= '0'; end if; - if line_count = 004 then vsync_out <= '1'; end if; - if line_count = 010 then vsync_out <= '0'; end if; + if dot_count = 010 then hsync_out <= '1'; + if line_count = 000 then vsync_out <= '1'; end if; + if line_count = 004 then vsync_out <= '0'; end if; + end if; + if dot_count = 048 then hsync_out <= '0'; end if; if wide = '0' then if dot_count = 510 then hblank <= '1'; end if; @@ -81,10 +82,11 @@ process(clk32) if line_count = 035 then vblank <= '0'; end if; end if; else - if dot_count = 010 then hsync_out <= '1'; end if; - if dot_count = 048 then hsync_out <= '0'; end if; - if line_count = 002 then vsync_out <= '1'; end if; - if line_count = 010 then vsync_out <= '0'; end if; + if dot_count = 010 then hsync_out <= '1'; + if line_count = 307 then vsync_out <= '1'; end if; + if line_count = 311 then vsync_out <= '0'; end if; + end if; + if dot_count = 048 then hsync_out <= '0'; end if; if wide = '0' then if dot_count = 480 then hblank <= '1'; end if;