From 73ef1dd59ec5e73849c7fa7909d16b8cd79dcf65 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Fri, 31 Aug 2018 20:18:03 +0800 Subject: [PATCH] Simplify IEC interconnections. --- C16.sv | 79 +++++++++---------------------------------- c1541/c1541_logic.vhd | 46 +++++++++++++++++++++---- c1541/c1541_sd.vhd | 11 +++++- c16.v | 19 +++++++++-- 4 files changed, 82 insertions(+), 73 deletions(-) diff --git a/C16.sv b/C16.sv index cd79998..70de01e 100644 --- a/C16.sv +++ b/C16.sv @@ -525,36 +525,20 @@ C16 c16 .ps2_key ( ps2_key ), - .IEC_DATAIN ( ~(c16_iec_data_i | c16_iec_data_o )), - .IEC_CLKIN ( ~(c16_iec_clk_i | c16_iec_clk_o )), - .IEC_ATNOUT ( c16_iec_atn_o ), - .IEC_DATAOUT ( c16_iec_data_o ), - .IEC_CLKOUT ( c16_iec_clk_o ), - .IEC_RESET ( iec_reset ), + .sound ( audio ), - .sound ( audio ) + .IEC_DATAIN ( c1541_iec_data_o ), + .IEC_CLKIN ( c1541_iec_clk_o ), + .IEC_ATNOUT ( c16_iec_atn_o ), + .IEC_DATAOUT ( c16_iec_data_o ), + .IEC_CLKOUT ( c16_iec_clk_o ), + .IEC_RESET ( c16_iec_reset_o ) ); wire c16_iec_atn_o; wire c16_iec_data_o; wire c16_iec_clk_o; - -reg c16_iec_data_i; -reg c16_iec_clk_i; - -always @(posedge clk_c16) begin - reg iec_data_d1,iec_data_d2; - reg iec_clk_d1,iec_clk_d2; - - iec_data_d1<=c1541_iec_data_o; - iec_clk_d1 <=c1541_iec_clk_o; - - iec_data_d2<=iec_data_d1; - iec_clk_d2 <=iec_clk_d1; - - c16_iec_data_i<=iec_data_d2; - c16_iec_clk_i <=iec_clk_d2; -end +wire c16_iec_reset_o; wire [4:0] audio; @@ -609,45 +593,13 @@ video_mixer #(456, 1) mixer /////////////////////////////////////////////////// wire led_disk; -wire iec_reset; wire c1541_iec_data_o; wire c1541_iec_clk_o; -reg c1541_iec_atn_i; -reg c1541_iec_data_i; -reg c1541_iec_clk_i; - -always @(posedge clk_sys) begin - reg iec_atn_d1,iec_atn_d2; - reg iec_data_d1,iec_data_d2; - reg iec_clk_d1,iec_clk_d2; - - iec_atn_d1 <=c16_iec_atn_o; - iec_data_d1<=c16_iec_data_o; - iec_clk_d1 <=c16_iec_clk_o; - - iec_atn_d2 <=iec_atn_d1; - iec_data_d2<=iec_data_d1; - iec_clk_d2 <=iec_clk_d1; - - c1541_iec_atn_i <=iec_atn_d2; - c1541_iec_data_i<=iec_data_d2; - c1541_iec_clk_i <=iec_clk_d2; -end - - -reg c1541_reset; -always @(posedge clk_sys) begin - reg rst; - rst <= iec_reset; - c1541_reset <= rst; -end - c1541_sd c1541_sd ( .clk32 (clk_sys), - .reset (c1541_reset), .c1541rom_clk(clk_sys), .c1541rom_addr(ioctl_addr[13:0]), @@ -658,12 +610,6 @@ c1541_sd c1541_sd .disk_readonly ( img_readonly ), .led (led_disk), - .iec_atn_i ( c1541_iec_atn_i ), - .iec_data_i ( c1541_iec_data_i | c1541_iec_data_o ), - .iec_clk_i ( c1541_iec_clk_i | c1541_iec_clk_o ), - .iec_data_o ( c1541_iec_data_o ), - .iec_clk_o ( c1541_iec_clk_o ), - .sd_lba(sd_lba), .sd_rd(sd_rd), .sd_wr(sd_wr), @@ -671,7 +617,14 @@ c1541_sd c1541_sd .sd_buff_addr(sd_buff_addr), .sd_buff_dout(sd_buff_dout), .sd_buff_din(sd_buff_din), - .sd_buff_wr(sd_buff_wr) + .sd_buff_wr(sd_buff_wr), + + .iec_reset_i( c16_iec_reset_o ), + .iec_atn_i ( c16_iec_atn_o ), + .iec_data_i ( c16_iec_data_o ), + .iec_clk_i ( c16_iec_clk_o ), + .iec_data_o ( c1541_iec_data_o ), + .iec_clk_o ( c1541_iec_clk_o ) ); endmodule diff --git a/c1541/c1541_logic.vhd b/c1541/c1541_logic.vhd index ee6ed7a..4260487 100644 --- a/c1541/c1541_logic.vhd +++ b/c1541/c1541_logic.vhd @@ -94,8 +94,36 @@ architecture SYN of c1541_logic is type t_byte_array is array(2047 downto 0) of std_logic_vector(7 downto 0); signal ram : t_byte_array; - + + signal sb_data : std_logic; + signal sb_clk : std_logic; + + signal iec_atn_d1 : std_logic; + signal iec_data_d1 : std_logic; + signal iec_clk_d1 : std_logic; + signal iec_atn_d2 : std_logic; + signal iec_data_d2 : std_logic; + signal iec_clk_d2 : std_logic; + signal iec_atn : std_logic; + signal iec_data : std_logic; + signal iec_clk : std_logic; + begin + process (clk_32M) begin + if rising_edge(clk_32M) then + iec_atn_d1 <=sb_atn_in; + iec_atn_d2 <=iec_atn_d1; + iec_atn <=iec_atn_d2; + + iec_data_d1<=sb_data_in; + iec_data_d2<=iec_data_d1; + iec_data <=iec_data_d2; + + iec_clk_d1 <=sb_clk_in; + iec_clk_d2 <=iec_clk_d1; + iec_clk <=iec_clk_d2; + end if; + end process; process (clk_32M, reset) variable count : std_logic_vector(4 downto 0) := (others => '0'); @@ -120,14 +148,18 @@ begin -- -- hook up UC1 ports -- + sb_data <= (uc1_pb_o(1) and not uc1_pb_oe_n(1)) or atn; + sb_clk <= uc1_pb_o(3) and not uc1_pb_oe_n(3); + atna <= uc1_pb_o(4); + uc1_pa_i(0) <= tr00_sense_n; - uc1_pb_i(0) <= not sb_data_in or (uc1_pb_o(1) and not uc1_pb_oe_n(1)) or atn; - sb_data_oe <= (uc1_pb_o(1) and not uc1_pb_oe_n(1)) or atn; - uc1_pb_i(2) <= not sb_clk_in or (uc1_pb_o(3) and not uc1_pb_oe_n(3)); - sb_clk_oe <= uc1_pb_o(3) and not uc1_pb_oe_n(3); - atna <= uc1_pb_o(4); + uc1_pb_i(0) <= not iec_data or sb_data; + uc1_pb_i(2) <= not iec_clk or sb_clk; + uc1_pb_i(7) <= not iec_atn; uc1_pb_i(6 downto 5) <= ds; - uc1_pb_i(7) <= not sb_atn_in; + + sb_data_oe <= sb_data; + sb_clk_oe <= sb_clk; -- -- hook up UC3 ports diff --git a/c1541/c1541_sd.vhd b/c1541/c1541_sd.vhd index 185cafa..3a0e68a 100644 --- a/c1541/c1541_sd.vhd +++ b/c1541/c1541_sd.vhd @@ -27,12 +27,12 @@ entity c1541_sd is port ( clk32 : in std_logic; - reset : in std_logic; disk_change : in std_logic; disk_readonly : in std_logic; drive_num : in std_logic_vector(1 downto 0) := "00"; + iec_reset_i : in std_logic; iec_atn_i : in std_logic; iec_data_i : in std_logic; iec_clk_i : in std_logic; @@ -114,10 +114,19 @@ architecture struct of c1541_sd is signal ch_timeout : integer := 0; signal prev_change : std_logic := '0'; signal ch_state : std_logic := '0'; + + signal reset, reset_r : std_logic; begin tr00_sense_n <= '1' when (track > "000000") else '0'; + process(clk32) begin + if rising_edge(clk32) then + reset_r <= iec_reset_i; + reset <= reset_r; + end if; + end process; + process(clk32) begin if rising_edge(clk32) then prev_change <= disk_change; diff --git a/c16.v b/c16.v index affc6c1..80ddaf9 100644 --- a/c16.v +++ b/c16.v @@ -196,12 +196,27 @@ assign c16_data=cpu_data&ted_data&DIN&keyport_data; // C16 data bus assign ADDR=c16_addr; assign DOUT=cpu_data; +reg iec_data; +reg iec_clk; +always @(posedge CLK28) begin + reg iec_data_d1,iec_data_d2; + reg iec_clk_d1,iec_clk_d2; + + iec_data_d1<=IEC_DATAIN; + iec_data_d2<=iec_data_d1; + iec_data <=iec_data_d2; + + iec_clk_d1 <=IEC_CLKIN; + iec_clk_d2 <=iec_clk_d1; + iec_clk <=iec_clk_d2; +end + // connect IEC bus assign port_in[5:0]=0; assign IEC_DATAOUT=port_out[0]; -assign port_in[7]=IEC_DATAIN; +assign port_in[7]=~(iec_data|port_out[0]); assign IEC_CLKOUT=port_out[1]; -assign port_in[6]=IEC_CLKIN; +assign port_in[6]=~(iec_clk|port_out[1]); assign IEC_ATNOUT=port_out[2]; assign IEC_RESET=sreset;