diff --git a/C16.qsf b/C16.qsf index c002e7a..90c982b 100644 --- a/C16.qsf +++ b/C16.qsf @@ -351,13 +351,15 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name QIP_FILE sys/sys.qip -set_global_assignment -name QIP_FILE pll2.qip set_global_assignment -name QIP_FILE c1541/c1541.qip set_global_assignment -name QIP_FILE t65/t65.qip set_global_assignment -name QIP_FILE sid8580/sid.qip set_global_assignment -name QIP_FILE sid6581/sid.qip +set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv set_global_assignment -name VHDL_FILE gen_rom.vhd set_global_assignment -name VHDL_FILE gen_dpram.vhd +set_global_assignment -name VHDL_FILE tap_fifo.vhd +set_global_assignment -name VHDL_FILE c1530.vhd set_global_assignment -name VERILOG_FILE mos8501.v set_global_assignment -name VERILOG_FILE mos6529.v set_global_assignment -name VERILOG_FILE colors_to_rgb.v diff --git a/C16.sv b/C16.sv index 3d1218b..ba71265 100644 --- a/C16.sv +++ b/C16.sv @@ -1,101 +1,101 @@ -//============================================================================ -// C16,Plus/4 -// -// Port to MiSTer -// Copyright (C) 2017,2018 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module emu -( - //Master input clock - input CLK_50M, - - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [44:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - output [7:0] VIDEO_ARX, - output [7:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) +//============================================================================ +// C16,Plus/4 +// +// Port to MiSTer +// Copyright (C) 2017,2018 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module emu +( + //Master input clock + input CLK_50M, + + //Async reset from top-level module. + //Can be used as initial reset. + input RESET, + + //Must be passed to hps_io module + inout [44:0] HPS_BUS, + + //Base video clock. Usually equals to CLK_SYS. + output CLK_VIDEO, + + //Multiple resolutions are supported using different CE_PIXEL rates. + //Must be based on CLK_VIDEO + output CE_PIXEL, + + //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. + output [7:0] VIDEO_ARX, + output [7:0] VIDEO_ARY, + + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, // = ~(VBlank | HBlank) output VGA_F1, output [1:0] VGA_SL, - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - input TAPE_IN, - - // SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, - output [12:0] SDRAM_A, - output [1:0] SDRAM_BA, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nCS, - output SDRAM_nCAS, - output SDRAM_nRAS, + + output LED_USER, // 1 - ON, 0 - OFF. + + // b[1]: 0 - LED status is system status OR'd with b[0] + // 1 - LED status is controled solely by b[0] + // hint: supply 2'b00 to let the system control the LED. + output [1:0] LED_POWER, + output [1:0] LED_DISK, + + output [15:0] AUDIO_L, + output [15:0] AUDIO_R, + output AUDIO_S, // 1 - signed audio samples, 0 - unsigned + output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) + input TAPE_IN, + + // SD-SPI + output SD_SCK, + output SD_MOSI, + input SD_MISO, + output SD_CS, + input SD_CD, + + //High latency DDR3 RAM interface + //Use for non-critical time purposes + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + //SDRAM interface with lower latency + output SDRAM_CLK, + output SDRAM_CKE, + output [12:0] SDRAM_A, + output [1:0] SDRAM_BA, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nCS, + output SDRAM_nCAS, + output SDRAM_nRAS, output SDRAM_nWE, input UART_CTS, @@ -114,543 +114,678 @@ module emu output [5:0] USER_OUT, input OSD_STATUS -); - +); + assign USER_OUT = '1; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; -assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0; - -assign LED_USER = ioctl_download | led_disk; -assign LED_DISK = 0; -assign LED_POWER = 0; - -assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; -assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; - -`include "build_id.v" -parameter CONF_STR1 = { - "C16;;", - "-;", - "F,PRG;", - "F,BIN,Load Cart(Plus/4);", - "-;", - "S,D64;", - "-;", - "O1,Aspect ratio,4:3,16:9;", - "O24,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;", - "O78,TV Standard,from Kernal,Force PAL,Force NTSC;", - "-;", - "ODE,SID card,Disabled,6581,8580;", - "-;", - "O5,Joysticks swap,No,Yes;", - "-;", - "O9,Model,C16,Plus/4;" -}; - -parameter CONF_STR2 = { - "6,Kernal,from boot.rom,Original;", - "R0,Reset;", - "J,Fire;", - "V,v",`BUILD_DATE -}; - -///////////////// CLOCKS //////////////////////// - -wire clk_sys; -wire clk_c16 = clk_x2 & clk_en; -wire clk_x2; - -pll pll -( - .refclk(CLK_50M), - .rst(0), - .outclk_0(clk_sys) -); - -wire locked; -pll2 pll2 -( - .refclk(CLK_50M), - .rst(0), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - .outclk_0(clk_x2), - .locked(locked) -); - -wire [63:0] reconfig_to_pll; -wire [63:0] reconfig_from_pll; -wire cfg_waitrequest; -reg cfg_write; -reg [5:0] cfg_address; -reg [31:0] cfg_data; - -pll_hdmi_cfg pll_hdmi_cfg -( - .mgmt_clk(CLK_50M), - .mgmt_reset(0), - .mgmt_waitrequest(cfg_waitrequest), - .mgmt_read(0), - .mgmt_readdata(), - .mgmt_write(cfg_write), - .mgmt_address(cfg_address), - .mgmt_writedata(cfg_data), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) -); - -always @(posedge CLK_50M) begin - reg pald = 0, pald2 = 0; - reg [2:0] state = 0; - - pald <= pal; - pald2 <= pald; - - cfg_write <= 0; - if(pald2 != pald) state <= 1; - - if(!cfg_waitrequest) begin - if(state) state<=state+1'd1; - case(state) - 1: begin - cfg_address <= 0; - cfg_data <= 0; - cfg_write <= 1; - end - 3: begin - cfg_address <= 7; - cfg_data <= pald2 ? 32'h15448515 : 32'h29E2B79B; - cfg_write <= 1; - end - 5: begin - cfg_address <= 2; - cfg_data <= 0; - cfg_write <= 1; - end - endcase - end -end - -reg clk_en = 0; -always @(negedge clk_x2) begin - reg lockedd; - - lockedd <= locked; - - clk_en <= ~clk_en; - if(~lockedd) clk_en <= 0; -end - - -///////////////// HPS /////////////////////////// - -wire [31:0] status; -wire [1:0] buttons; - -wire [15:0] joya, joyb; -wire [10:0] ps2_key; - -wire ioctl_download; -wire [7:0] ioctl_index; -wire ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; -wire forced_scandoubler; - -wire [31:0] sd_lba; -wire sd_rd; -wire sd_wr; -wire sd_ack; -wire [8:0] sd_buff_addr; -wire [7:0] sd_buff_dout; -wire [7:0] sd_buff_din; -wire sd_buff_wr; -wire img_mounted; -wire img_readonly; - -hps_io #(.STRLEN(($size(CONF_STR1)>>3)+($size(CONF_STR2)>>3)+1)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - - .conf_str({CONF_STR1, rom_loaded ? "O" : "+", CONF_STR2}), - - .buttons(buttons), - .status(status), - .forced_scandoubler(forced_scandoubler), - - .ps2_key(ps2_key), - - .ioctl_download(ioctl_download), - .ioctl_index(ioctl_index), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - - .sd_lba(sd_lba), - .sd_rd(sd_rd), - .sd_wr(sd_wr), - .sd_ack(sd_ack), - .sd_buff_addr(sd_buff_addr), - .sd_buff_dout(sd_buff_dout), - .sd_buff_din(sd_buff_din), - .sd_buff_wr(sd_buff_wr), - .img_mounted(img_mounted), - .img_readonly(img_readonly), - - .joystick_0(joya), - .joystick_1(joyb) -); - -///////////////// RESET ///////////////////////// - -wire sys_reset = RESET | status[0] | buttons[1]; -wire reset = sys_reset | cart_reset; - -///////////////// RAM ///////////////////////// - -reg [15:0] dl_addr; -reg [7:0] dl_data; -reg dl_wr; -reg model; - -always @(posedge clk_sys) begin - reg old_download = 0; - reg [3:0] state = 0; - reg [15:0] addr; - - if(reset) model <= status[9]; - - dl_wr <= 0; - old_download <= ioctl_download; - - if(ioctl_download && (ioctl_index == 1)) begin - state <= 0; - if(ioctl_wr) begin - if(ioctl_addr == 0) addr[7:0] <= ioctl_dout; - else if(ioctl_addr == 1) addr[15:8] <= ioctl_dout; - else begin - dl_addr <= addr; - dl_data <= ioctl_dout; - dl_wr <= 1; - addr <= addr + 1'd1; - end - end - end - - if(old_download && ~ioctl_download && (ioctl_index == 1)) state <= 1; - if(state) state <= state + 1'd1; - - case(state) - 1: begin dl_addr <= 16'h2d; dl_data <= addr[7:0]; dl_wr <= 1; end - 3: begin dl_addr <= 16'h2e; dl_data <= addr[15:8]; dl_wr <= 1; end - 5: begin dl_addr <= 16'h2f; dl_data <= addr[7:0]; dl_wr <= 1; end - 7: begin dl_addr <= 16'h30; dl_data <= addr[15:8]; dl_wr <= 1; end - 9: begin dl_addr <= 16'h31; dl_data <= addr[7:0]; dl_wr <= 1; end - 11: begin dl_addr <= 16'h32; dl_data <= addr[15:8]; dl_wr <= 1; end - 13: begin dl_addr <= 16'h9d; dl_data <= addr[7:0]; dl_wr <= 1; end - 15: begin dl_addr <= 16'h9e; dl_data <= addr[15:8]; dl_wr <= 1; end - endcase -end - -wire [7:0] ram_dout; -gen_dpram #(16) main_ram -( - .clock_a(clk_sys), - .address_a(dl_addr), - .data_a(dl_data), - .wren_a(dl_wr), - - .clock_b(clk_c16), - .address_b(c16_addr), - .data_b(c16_dout), - .wren_b(ram_we), - .q_b(ram_dout), - .cs_b(~cs_ram) -); - -reg ram_we; -always @(posedge clk_c16) begin - reg old_cs; - ram_we <= 0; - - old_cs <= cs_ram; - if(old_cs & ~cs_ram) ram_we <= ~c16_rnw; -end - -///////////////// ROM ///////////////////////// - -reg rom_loaded =0; -always @(posedge clk_sys) if(ioctl_wr && (ioctl_addr[24:14]==1) && !ioctl_index) rom_loaded <=1; - -// Kernal rom -wire [7:0] kernal0_dout; -gen_rom #("roms/c16_kernal.mif") kernal0 -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==1) && !ioctl_index), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(kernal0_dout), - .cs(~cs1 && (!romh || kern) && ~status[6]) -); - -wire [7:0] kernal1_dout; -gen_rom #("roms/c16_kernal.mif") kernal1 -( - .wrclock(clk_sys), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(kernal1_dout), - .cs(~cs1 && (!romh || kern) && status[6]) -); - -// Basic rom -wire [7:0] basic_dout; -gen_rom #("roms/c16_basic.mif") basic -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==2) && !ioctl_index), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(basic_dout), - .cs(~cs0 && !roml) -); - -// Func low -wire [7:0] fl_dout; -gen_rom #("roms/3-plus-1_low.mif") funcl -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==3) && !ioctl_index), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(fl_dout), - .cs(~cs0 && roml==2) -); - -// Func high -wire [7:0] fh_dout; -gen_rom #("roms/3-plus-1_high.mif") funch -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==4) && !ioctl_index), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(fh_dout), - .cs(~cs1 && romh==2 && ~kern) -); - -// Cart low -wire [7:0] cartl_dout; -gen_rom cart_l -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==0) && (ioctl_index==2)), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(cartl_dout), - .cs(~cs0 && cartl && roml==1) -); - -// Cart high -wire [7:0] carth_dout; -gen_rom cart_h -( - .wrclock(clk_sys), - .wraddress(ioctl_addr[13:0]), - .data(ioctl_dout), - .wren(ioctl_wr && (ioctl_addr[24:14]==1) && (ioctl_index==2)), - - .rdclock(clk_c16), - .rdaddress(c16_addr[13:0]), - .q(carth_dout), - .cs(~cs1 && carth && romh==1 && ~kern) -); - -wire cart_reset = model & ioctl_download & (ioctl_index==2); -reg cartl,carth; -always @(posedge clk_sys) begin - if(sys_reset) {cartl,carth} <= 0; - if(ioctl_wr && (ioctl_addr[24:14]==0) && (ioctl_index==2)) cartl <= 1; - if(ioctl_wr && (ioctl_addr[24:14]==1) && (ioctl_index==2)) carth <= 1; -end - -wire kern = (c16_addr[15:8]==8'hFC); - -reg [1:0] roml, romh; -always @(posedge clk_c16) begin - reg old_cs; - - old_cs <= cs_io; - - if(reset) {romh,roml} <= 0; - else if(model && old_cs && ~cs_io && ~c16_rnw && c16_addr[15:4] == 12'hFDD) {romh,roml} <= c16_addr[3:0]; -end - -/////////////////////////////////////////////////// - -wire [7:0] c16_dout; -wire [15:0] c16_addr; -wire c16_rnw; -wire pal; - -wire [7:0] c16_din = ram_dout & kernal0_dout & kernal1_dout & basic_dout & fh_dout & fl_dout & cartl_dout & carth_dout; - -wire cs_ram,cs0,cs1,cs_io; -C16 c16 -( - .CLK28 ( clk_c16 ), // NTSC 28.636299, PAL 28.384615 - .RESET ( reset ), - .WAIT ( 0 ), - .PAL ( pal ), - - .CE_PIX ( ce_pix ), - .HSYNC ( hs ), - .VSYNC ( vs ), - .HBLANK ( hblank ), - .VBLANK ( vblank ), - .RED ( r ), - .GREEN ( g ), - .BLUE ( b ), - .tvmode ( status[8:7] ), - - .RnW ( c16_rnw ), - .ADDR ( c16_addr ), - .DOUT ( c16_dout ), - .DIN ( c16_din ), - .CS_RAM ( cs_ram ), - .CS0 ( cs0 ), - .CS1 ( cs1 ), - .CS_IO ( cs_io ), - - .JOY0 ( status[5] ? joyb[4:0] : joya[4:0] ), - .JOY1 ( status[5] ? joya[4:0] : joyb[4:0] ), - - .ps2_key ( ps2_key ), - - .sid_type( status[14:13] ), - .sound ( AUDIO_L ), - - .IEC_DATAIN ( c1541_iec_data_o ), - .IEC_CLKIN ( c1541_iec_clk_o ), - .IEC_ATNOUT ( c16_iec_atn_o ), - .IEC_DATAOUT ( c16_iec_data_o ), - .IEC_CLKOUT ( c16_iec_clk_o ), - .IEC_RESET ( c16_iec_reset_o ) -); - -wire c16_iec_atn_o; -wire c16_iec_data_o; -wire c16_iec_clk_o; -wire c16_iec_reset_o; - -assign AUDIO_R = AUDIO_L; -assign AUDIO_MIX = 0; -assign AUDIO_S = 1; - -wire hs, vs, hblank, vblank, ce_pix; -wire [3:0] r,g,b; - -wire [2:0] scale = status[4:2]; -wire [2:0] sl = scale ? scale - 1'd1 : 3'd0; - -assign VGA_F1 = 0; -assign VGA_SL = sl[1:0]; - -assign CLK_VIDEO = clk_x2; - -reg ce_vid; -always @(posedge CLK_VIDEO) begin - reg old_ce; - - old_ce <= ce_pix; - ce_vid <= ~old_ce & ce_pix; -end - -video_mixer #(456, 1) mixer -( - .clk_sys(CLK_VIDEO), - - .ce_pix(ce_vid), - .ce_pix_out(CE_PIXEL), - - .hq2x(scale == 1), - .scanlines(0), - .scandoubler(scale || forced_scandoubler), - - .R(r), - .G(g), - .B(b), - - .mono(0), - - .HSync(~hs), - .VSync(~vs), - .HBlank(hblank), - .VBlank(vblank), - - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .VGA_DE(VGA_DE) -); - -/////////////////////////////////////////////////// - -wire led_disk; - -wire c1541_iec_data_o; -wire c1541_iec_clk_o; - -c1541_sd c1541_sd -( - .clk32 (clk_sys), - - .c1541rom_clk(clk_sys), - .c1541rom_addr(ioctl_addr[13:0]), - .c1541rom_data(ioctl_dout), - .c1541rom_wr(ioctl_wr && (ioctl_addr[24:14] == 0) && !ioctl_index), - - .disk_change ( img_mounted ), - .disk_readonly ( img_readonly ), - .led (led_disk), - - .sd_lba(sd_lba), - .sd_rd(sd_rd), - .sd_wr(sd_wr), - .sd_ack(sd_ack), - .sd_buff_addr(sd_buff_addr), - .sd_buff_dout(sd_buff_dout), - .sd_buff_din(sd_buff_din), - .sd_buff_wr(sd_buff_wr), - - .iec_reset_i( c16_iec_reset_o ), - .iec_atn_i ( c16_iec_atn_o ), - .iec_data_i ( c16_iec_data_o ), - .iec_clk_i ( c16_iec_clk_o ), - .iec_data_o ( c1541_iec_data_o ), - .iec_clk_o ( c1541_iec_clk_o ) -); - -endmodule +assign {UART_RTS, UART_TXD, UART_DTR} = 0; +assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; +assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; + +assign LED_USER = ioctl_download | led_disk | tape_led; +assign LED_DISK = 0; +assign LED_POWER = 0; + +assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; +assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; + +`include "build_id.v" +parameter CONF_STR1 = { + "C16;;", + "-;", + "F,PRG;", + "F,BIN,Load Cart(Plus/4);", + "-;", + "S,D64;", + "-;", + "F,TAP,Load Tape;", + "RG,Tape Play/Stop;", + "OH,Tape Sound,Off,On;", + "-;", + "O1,Aspect ratio,4:3,16:9;", + "O24,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;", + "O78,TV Standard,from Kernal,Force PAL,Force NTSC;", + "-;", + "ODE,SID card,Disabled,6581,8580;", + "-;", + "O5,Joysticks swap,No,Yes;", + "-;", + "O9,Model,C16,Plus/4;" +}; + +parameter CONF_STR2 = { + "6,Kernal,from boot.rom,Original;", + "R0,Reset;", + "J,Fire;", + "V,v",`BUILD_DATE +}; + +///////////////// CLOCKS //////////////////////// + +wire clk_sys; +wire clk_c16 = clk_sys & clk_en; +wire locked; + +pll pll +( + .refclk(CLK_50M), + .outclk_0(clk_sys), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + .locked(locked) +); + +wire [63:0] reconfig_to_pll; +wire [63:0] reconfig_from_pll; +wire cfg_waitrequest; +reg cfg_write; +reg [5:0] cfg_address; +reg [31:0] cfg_data; + +pll_hdmi_cfg pll_hdmi_cfg +( + .mgmt_clk(CLK_50M), + .mgmt_reset(0), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_read(0), + .mgmt_readdata(), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) +); + +always @(posedge CLK_50M) begin + reg pald = 0, pald2 = 0; + reg [2:0] state = 0; + + pald <= pal; + pald2 <= pald; + + cfg_write <= 0; + if(pald2 != pald) state <= 1; + + if(!cfg_waitrequest) begin + if(state) state<=state+1'd1; + case(state) + 1: begin + cfg_address <= 0; + cfg_data <= 0; + cfg_write <= 1; + end + 3: begin + cfg_address <= 7; + cfg_data <= pald2 ? 343828281 : 702807832; + cfg_write <= 1; + end + 5: begin + cfg_address <= 2; + cfg_data <= 0; + cfg_write <= 1; + end + endcase + end +end + +reg clk_en = 0; +always @(negedge clk_sys) begin + reg lockedd; + + lockedd <= locked; + clk_en <= ~clk_en; + if(~lockedd) clk_en <= 0; +end + + +///////////////// HPS /////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; + +wire [15:0] joya, joyb; +wire [10:0] ps2_key; + +wire ioctl_download; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; +wire forced_scandoubler; + +wire [31:0] sd_lba; +wire sd_rd; +wire sd_wr; +wire sd_ack; +wire [8:0] sd_buff_addr; +wire [7:0] sd_buff_dout; +wire [7:0] sd_buff_din; +wire sd_buff_wr; +wire img_mounted; +wire img_readonly; +reg ioctl_wait = 0; + +hps_io #(.STRLEN(($size(CONF_STR1)>>3)+($size(CONF_STR2)>>3)+1)) hps_io +( + .clk_sys(clk_sys), + .HPS_BUS(HPS_BUS), + + .conf_str({CONF_STR1, rom_loaded ? "O" : "+", CONF_STR2}), + + .buttons(buttons), + .status(status), + .forced_scandoubler(forced_scandoubler), + + .ps2_key(ps2_key), + + .ioctl_download(ioctl_download), + .ioctl_index(ioctl_index), + .ioctl_wr(ioctl_wr), + .ioctl_addr(ioctl_addr), + .ioctl_dout(ioctl_dout), + .ioctl_wait(ioctl_wait), + + .sd_lba(sd_lba), + .sd_rd(sd_rd), + .sd_wr(sd_wr), + .sd_ack(sd_ack), + .sd_buff_addr(sd_buff_addr), + .sd_buff_dout(sd_buff_dout), + .sd_buff_din(sd_buff_din), + .sd_buff_wr(sd_buff_wr), + .img_mounted(img_mounted), + .img_readonly(img_readonly), + + .joystick_0(joya), + .joystick_1(joyb) +); + +///////////////// RESET ///////////////////////// + +wire sys_reset = RESET | status[0] | buttons[1]; +wire reset = sys_reset | cart_reset; + +///////////////// RAM ///////////////////////// + +reg [15:0] dl_addr; +reg [7:0] dl_data; +reg dl_wr; +reg model; + +always @(posedge clk_sys) begin + reg old_download = 0; + reg [3:0] state = 0; + reg [15:0] addr; + + if(reset) model <= status[9]; + + dl_wr <= 0; + old_download <= ioctl_download; + + if(ioctl_download && (ioctl_index == 1)) begin + state <= 0; + if(ioctl_wr) begin + if(ioctl_addr == 0) addr[7:0] <= ioctl_dout; + else if(ioctl_addr == 1) addr[15:8] <= ioctl_dout; + else begin + dl_addr <= addr; + dl_data <= ioctl_dout; + dl_wr <= 1; + addr <= addr + 1'd1; + end + end + end + + if(old_download && ~ioctl_download && (ioctl_index == 1)) state <= 1; + if(state) state <= state + 1'd1; + + case(state) + 1: begin dl_addr <= 16'h2d; dl_data <= addr[7:0]; dl_wr <= 1; end + 3: begin dl_addr <= 16'h2e; dl_data <= addr[15:8]; dl_wr <= 1; end + 5: begin dl_addr <= 16'h2f; dl_data <= addr[7:0]; dl_wr <= 1; end + 7: begin dl_addr <= 16'h30; dl_data <= addr[15:8]; dl_wr <= 1; end + 9: begin dl_addr <= 16'h31; dl_data <= addr[7:0]; dl_wr <= 1; end + 11: begin dl_addr <= 16'h32; dl_data <= addr[15:8]; dl_wr <= 1; end + 13: begin dl_addr <= 16'h9d; dl_data <= addr[7:0]; dl_wr <= 1; end + 15: begin dl_addr <= 16'h9e; dl_data <= addr[15:8]; dl_wr <= 1; end + endcase +end + +wire [7:0] ram_dout; +gen_dpram #(16) main_ram +( + .clock_a(clk_sys), + .address_a(dl_addr), + .data_a(dl_data), + .wren_a(dl_wr), + + .clock_b(clk_c16), + .address_b(c16_addr), + .data_b(c16_dout), + .wren_b(ram_we), + .q_b(ram_dout), + .cs_b(~cs_ram) +); + +reg ram_we; +always @(posedge clk_c16) begin + reg old_cs; + ram_we <= 0; + + old_cs <= cs_ram; + if(old_cs & ~cs_ram) ram_we <= ~c16_rnw; +end + +///////////////// ROM ///////////////////////// + +reg rom_loaded =0; +always @(posedge clk_sys) if(ioctl_wr && (ioctl_addr[24:14]==1) && !ioctl_index) rom_loaded <=1; + +// Kernal rom +wire [7:0] kernal0_dout; +gen_rom #("roms/c16_kernal.mif") kernal0 +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==1) && !ioctl_index), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(kernal0_dout), + .cs(~cs1 && (!romh || kern) && ~status[6]) +); + +wire [7:0] kernal1_dout; +gen_rom #("roms/c16_kernal.mif") kernal1 +( + .wrclock(clk_sys), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(kernal1_dout), + .cs(~cs1 && (!romh || kern) && status[6]) +); + +// Basic rom +wire [7:0] basic_dout; +gen_rom #("roms/c16_basic.mif") basic +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==2) && !ioctl_index), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(basic_dout), + .cs(~cs0 && !roml) +); + +// Func low +wire [7:0] fl_dout; +gen_rom #("roms/3-plus-1_low.mif") funcl +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==3) && !ioctl_index), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(fl_dout), + .cs(~cs0 && roml==2) +); + +// Func high +wire [7:0] fh_dout; +gen_rom #("roms/3-plus-1_high.mif") funch +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==4) && !ioctl_index), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(fh_dout), + .cs(~cs1 && romh==2 && ~kern) +); + +// Cart low +wire [7:0] cartl_dout; +gen_rom cart_l +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==0) && (ioctl_index==2)), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(cartl_dout), + .cs(~cs0 && cartl && roml==1) +); + +// Cart high +wire [7:0] carth_dout; +gen_rom cart_h +( + .wrclock(clk_sys), + .wraddress(ioctl_addr[13:0]), + .data(ioctl_dout), + .wren(ioctl_wr && (ioctl_addr[24:14]==1) && (ioctl_index==2)), + + .rdclock(clk_c16), + .rdaddress(c16_addr[13:0]), + .q(carth_dout), + .cs(~cs1 && carth && romh==1 && ~kern) +); + +wire cart_reset = model & ioctl_download & (ioctl_index==2); +reg cartl,carth; +always @(posedge clk_sys) begin + if(sys_reset) {cartl,carth} <= 0; + if(ioctl_wr && (ioctl_addr[24:14]==0) && (ioctl_index==2)) cartl <= 1; + if(ioctl_wr && (ioctl_addr[24:14]==1) && (ioctl_index==2)) carth <= 1; +end + +wire kern = (c16_addr[15:8]==8'hFC); + +reg [1:0] roml, romh; +always @(posedge clk_c16) begin + reg old_cs; + + old_cs <= cs_io; + + if(reset) {romh,roml} <= 0; + else if(model && old_cs && ~cs_io && ~c16_rnw && c16_addr[15:4] == 12'hFDD) {romh,roml} <= c16_addr[3:0]; +end + +/////////////////////////////////////////////////// + +wire [7:0] c16_dout; +wire [15:0] c16_addr; +wire c16_rnw; +wire pal; + +wire [7:0] c16_din = ram_dout & kernal0_dout & kernal1_dout & basic_dout & fh_dout & fl_dout & cartl_dout & carth_dout & cass_dout; + +wire cs_ram,cs0,cs1,cs_io; +C16 c16 +( + .CLK28 ( clk_c16 ), // NTSC 28.636299, PAL 28.384615 + .RESET ( reset ), + .WAIT ( 0 ), + .PAL ( pal ), + + .CE_PIX ( ce_pix ), + .HSYNC ( hs ), + .VSYNC ( vs ), + .HBLANK ( hblank ), + .VBLANK ( vblank ), + .RED ( r ), + .GREEN ( g ), + .BLUE ( b ), + .tvmode ( status[8:7] ), + + .RnW ( c16_rnw ), + .ADDR ( c16_addr ), + .DOUT ( c16_dout ), + .DIN ( c16_din ), + .CS_RAM ( cs_ram ), + .CS0 ( cs0 ), + .CS1 ( cs1 ), + .CS_IO ( cs_io ), + + .cass_mtr( cass_motor ), + .cass_in ( cass_do ), + .cass_aud( cass_do & status[17] & tap_play), + + .JOY0 ( status[5] ? joyb[4:0] : joya[4:0] ), + .JOY1 ( status[5] ? joya[4:0] : joyb[4:0] ), + + .ps2_key ( ps2_key ), + + .sid_type( status[14:13] ), + .sound ( AUDIO_L ), + + .IEC_DATAIN ( c1541_iec_data_o ), + .IEC_CLKIN ( c1541_iec_clk_o ), + .IEC_ATNOUT ( c16_iec_atn_o ), + .IEC_DATAOUT ( c16_iec_data_o ), + .IEC_CLKOUT ( c16_iec_clk_o ), + .IEC_RESET ( c16_iec_reset_o ) +); + +wire c16_iec_atn_o; +wire c16_iec_data_o; +wire c16_iec_clk_o; +wire c16_iec_reset_o; + +assign AUDIO_R = AUDIO_L; +assign AUDIO_MIX = 0; +assign AUDIO_S = 1; + +wire hs, vs, hblank, vblank, ce_pix; +wire [3:0] r,g,b; + +wire [2:0] scale = status[4:2]; +wire [2:0] sl = scale ? scale - 1'd1 : 3'd0; + +assign VGA_F1 = 0; +assign VGA_SL = sl[1:0]; + +assign CLK_VIDEO = clk_sys; + +reg ce_vid; +always @(posedge CLK_VIDEO) begin + reg old_ce; + + old_ce <= ce_pix; + ce_vid <= ~old_ce & ce_pix; +end + +video_mixer #(456, 1) mixer +( + .clk_sys(CLK_VIDEO), + + .ce_pix(ce_vid), + .ce_pix_out(CE_PIXEL), + + .hq2x(scale == 1), + .scanlines(0), + .scandoubler(scale || forced_scandoubler), + + .R(r), + .G(g), + .B(b), + + .mono(0), + + .HSync(~hs), + .VSync(~vs), + .HBlank(hblank), + .VBlank(vblank), + + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .VGA_DE(VGA_DE) +); + +/////////////////////////////////////////////////// + +wire led_disk; + +wire c1541_iec_data_o; +wire c1541_iec_clk_o; + +c1541_sd c1541_sd +( + .clk_c1541(clk_sys & ce_c1541), + .clk_sys(clk_sys), + + .rom_addr(ioctl_addr[13:0]), + .rom_data(ioctl_dout), + .rom_wr(ioctl_wr && (ioctl_addr[24:14] == 0) && !ioctl_index), + .rom_std(status[6]), + + .disk_change(img_mounted ), + .disk_readonly(img_readonly ), + .led(led_disk), + + .sd_lba(sd_lba), + .sd_rd(sd_rd), + .sd_wr(sd_wr), + .sd_ack(sd_ack), + .sd_buff_addr(sd_buff_addr), + .sd_buff_dout(sd_buff_dout), + .sd_buff_din(sd_buff_din), + .sd_buff_wr(sd_buff_wr), + + .iec_reset_i(c16_iec_reset_o), + .iec_atn_i(c16_iec_atn_o), + .iec_data_i(c16_iec_data_o), + .iec_clk_i(c16_iec_clk_o), + .iec_data_o(c1541_iec_data_o), + .iec_clk_o(c1541_iec_clk_o) +); + +reg ce_c1541; +always @(negedge clk_sys) begin + int sum = 0; + int msum; + + msum <= pal ? 56750336 : 57272720; + + ce_c1541 <= 0; + sum = sum + 32000000; + if(sum >= msum) begin + sum = sum - msum; + ce_c1541 <= 1; + end +end + + +/////////////////////////////////////////////////// + +assign DDRAM_CLK = clk_sys; +ddram ddram +( + .*, + .addr((ioctl_download & tap_load) ? ioctl_addr : tap_play_addr), + .dout(tap_data), + .din(ioctl_dout), + .we(tap_wr), + .rd(tap_rd), + .ready(tap_data_ready) +); + +reg tap_wr; +always @(posedge clk_sys) begin + reg old_reset; + + old_reset <= reset; + if(~old_reset && reset) ioctl_wait <= 0; + + tap_wr <= 0; + if(ioctl_wr && tap_load) begin + ioctl_wait <= 1; + tap_wr <= 1; + end + else if(~tap_wr & ioctl_wait && tap_data_ready) begin + ioctl_wait <= 0; + end +end + + +wire [7:0] cass_dout = {5'b11111, cs_io | (c16_addr[8:4] != 'h11) | ~tap_play, 2'b11}; + +reg tap_rd; +reg [24:0] tap_play_addr; +reg [24:0] tap_last_addr; +wire [7:0] tap_data; +wire tap_data_ready; +reg tap_reset; +reg tap_wrreq; +wire tap_wrfull; +wire tap_empty; +reg tap_loaded; +reg tap_play; +wire tap_play_btn = status[16]; +wire tap_load = (ioctl_index == 4); + +always @(posedge clk_sys) begin + reg tap_play_btnD; + reg tap_cycle = 0; + reg ioctl_downloadD; + + tap_play_btnD <= tap_play_btn; + tap_loaded <= (tap_play_addr < tap_last_addr); + ioctl_downloadD <= ioctl_download; + + if(reset) begin + tap_play_addr <= 0; + tap_last_addr <= 0; + tap_play <= 0; + tap_reset <= 1; + tap_rd <= 0; + tap_cycle <= 0; + end + else begin + if (~ioctl_download & ioctl_downloadD & tap_load) tap_play <= 1; + if (tap_loaded & ~tap_play_btnD & tap_play_btn) tap_play <= ~tap_play; + if (tap_empty) tap_play <= 0; + + tap_rd <= 0; + tap_wrreq <= 0; + + if(tap_cycle) begin + if(~tap_rd & tap_data_ready) begin + tap_play_addr <= tap_play_addr + 1'd1; + tap_cycle <= 0; + tap_wrreq <= 1; + end + end + else begin + if(tap_play & ~tap_wrfull & tap_loaded) begin + tap_rd <= 1; + tap_cycle <= 1; + end + end + + tap_reset <= 0; + if(ioctl_download && tap_load) begin + tap_play <= 0; + tap_play_addr <= 0; + tap_last_addr <= ioctl_addr+1'd1; + tap_reset <= 1; + tap_cycle <= 0; + end + end +end + +reg [26:0] act_cnt; +always @(posedge clk_sys) act_cnt <= act_cnt + (tap_play ? 4'd8 : 4'd1); +wire tape_led = tap_loaded && (act_cnt[26] ? (~(tap_play & cass_motor) && act_cnt[25:18] > act_cnt[7:0]) : act_cnt[25:18] <= act_cnt[7:0]); + +wire cass_motor; +wire cass_do; + +c1530 c1530 +( + .clk32(clk_sys), + .clk_freq(56750336), + .restart_tape(tap_reset), + .cpu_freq(886724), + .host_tap_in(tap_data), + .host_tap_wrreq(tap_wrreq), + .tap_fifo_wrfull(tap_wrfull), + .tap_fifo_error(tap_empty), + .play(~cass_motor), + .DO(cass_do) +); + +endmodule diff --git a/C16_Q13.qsf b/C16_Q13.qsf index ac4e24b..ae016fb 100644 --- a/C16_Q13.qsf +++ b/C16_Q13.qsf @@ -359,13 +359,15 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name QIP_FILE sys/sys_q13.qip -set_global_assignment -name QIP_FILE pll2_q13.qip set_global_assignment -name QIP_FILE c1541/c1541.qip set_global_assignment -name QIP_FILE t65/t65.qip set_global_assignment -name QIP_FILE sid8580/sid.qip set_global_assignment -name QIP_FILE sid6581/sid.qip +set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv set_global_assignment -name VHDL_FILE gen_rom.vhd set_global_assignment -name VHDL_FILE gen_dpram.vhd +set_global_assignment -name VHDL_FILE tap_fifo.vhd +set_global_assignment -name VHDL_FILE c1530.vhd set_global_assignment -name VERILOG_FILE mos8501.v set_global_assignment -name VERILOG_FILE mos6529.v set_global_assignment -name VERILOG_FILE colors_to_rgb.v diff --git a/c1530.vhd b/c1530.vhd new file mode 100644 index 0000000..34163b6 --- /dev/null +++ b/c1530.vhd @@ -0,0 +1,174 @@ +--------------------------------------------------------------------------------- +-- Commodore 1530 to SD card host (read only) by Dar (darfpga@aol.fr) 25-Mars-2019 +-- http://darfpga.blogspot.fr +-- also darfpga on sourceforge +-- +-- tap/wav player +-- Converted to 8 bit FIFO - Slingshot +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity c1530 is +port( + clk32 : in std_logic; + restart_tape : in std_logic; -- keep to 1 to long enough to clear fifo + -- reset tap header bytes skip counter + + clk_freq : in std_logic_vector(31 downto 0); + cpu_freq : in std_logic_vector(31 downto 0); + + host_tap_in : in std_logic_vector(7 downto 0); -- 8bits fifo input + host_tap_wrreq : in std_logic; -- set to 1 for 1 clk32 to write 1 word + tap_fifo_wrfull : out std_logic; -- do not write when fifo tap_fifo_full = 1 + + tap_fifo_error : out std_logic; -- fifo fall empty (unrecoverable error) + + play : in std_logic; -- 1 = read tape, 0 = stop reading + do : buffer std_logic -- tape signal out + +); +end c1530; + +architecture struct of c1530 is + +signal tap_player_tick_cnt : std_logic_vector( 5 downto 0); +signal tap_dword : std_logic_vector(31 downto 0); +signal wave_cnt : std_logic_vector(23 downto 0); +signal wave_len : std_logic_vector(23 downto 0); + +signal tap_fifo_do : std_logic_vector(7 downto 0); +signal tap_fifo_rdreq : std_logic; +signal tap_fifo_empty : std_logic; +signal get_24bits_len : std_logic; +signal start_bytes : std_logic_vector(7 downto 0); +signal skip_bytes : std_logic; +signal playing : std_logic; + +signal tap_mode : std_logic_vector(1 downto 0); + +begin + +-- for wav mode use large depth fifo (eg 512 x 32bits) +-- for tap mode fifo may be smaller (eg 16 x 32bits) +tap_fifo_inst : entity work.tap_fifo +port map( + aclr => restart_tape, + data => host_tap_in, + clock => clk32, + rdreq => tap_fifo_rdreq, + wrreq => host_tap_wrreq, + q => tap_fifo_do, + empty => tap_fifo_empty, + full => tap_fifo_wrfull +); + +process(clk32, restart_tape) +variable + sum : std_logic_vector(31 downto 0); +begin + + if restart_tape = '1' then + + start_bytes <= X"00"; + skip_bytes <= '1'; + tap_player_tick_cnt <= (others => '0'); + wave_len <= (others => '0'); + wave_cnt <= (others => '0'); + get_24bits_len <= '0'; + playing <= '0'; + do <= '1'; + + tap_fifo_rdreq <='0'; + tap_fifo_error <='0'; -- run out of data + + elsif rising_edge(clk32) then + + tap_fifo_rdreq <= '0'; + if playing = '0' then + tap_fifo_error <= '0'; + wave_cnt <= (others => '0'); + wave_len <= (others => '0'); + tap_player_tick_cnt <= (others => '0'); + end if; + + if play = '1' then playing <= '1'; end if; + if playing = '1' then + + tap_player_tick_cnt <= tap_player_tick_cnt + 1; + sum := sum + cpu_freq; + if sum >= clk_freq then + sum := sum - clk_freq; + if skip_bytes = '0' then + if tap_mode < 2 then + -- square wave period (1/2 duty cycle not mendatory, only falling edge matter) + if wave_cnt > '0'&wave_len(10 downto 1) then + do <= '1'; + else + do <= '0'; + end if; + end if; + + tap_player_tick_cnt <= (others => '0'); + wave_cnt <= wave_cnt + 1; + + if wave_cnt >= wave_len then + wave_cnt <= (others => '0'); + if tap_mode = 2 then + do <= not do; + end if; + if play = '0' then + playing <= '0'; + do <= '0'; + else + if tap_fifo_empty = '1' then + tap_fifo_error <= '1'; + else + tap_fifo_rdreq <= '1'; + if tap_fifo_do = x"00" then + wave_len <= x"000100"; -- interpret data x00 for mode 0 + get_24bits_len <= tap_mode(0) or tap_mode(1); + else + wave_len <= '0'&x"000" & tap_fifo_do & "000"; + end if; + end if; + end if; + end if; + end if; + end if; + + -- catch 24bits wave_len for data x00 in tap mode 1 + if get_24bits_len = '1' and skip_bytes = '0' and tap_player_tick_cnt(0) = '1' then + if tap_player_tick_cnt = 5 then + get_24bits_len <= '0'; + end if; + if tap_fifo_empty = '1' then + tap_fifo_error <= '1'; + else + tap_fifo_rdreq <= '1'; + wave_len <= tap_fifo_do & wave_len(23 downto 8); + end if; + end if; + + -- skip tap header bytes + if skip_bytes = '1' and tap_fifo_empty = '0' and tap_player_tick_cnt(0) = '1' then + tap_fifo_rdreq <= '1'; + if start_bytes = 13 then + tap_mode <= tap_fifo_do(1 downto 0); + end if; + if start_bytes < 20 then + start_bytes <= start_bytes + 1; + else + skip_bytes <= '0'; + end if; + end if; + + end if; -- play tap mode + + end if; -- clk32 +end process; + +end struct; diff --git a/c16.v b/c16.v index 984bfb3..b984ceb 100644 --- a/c16.v +++ b/c16.v @@ -56,6 +56,10 @@ module C16 output CS1, output CS_IO, + output cass_mtr, + input cass_in, + input cass_aud, + input [4:0] JOY0, input [4:0] JOY1, @@ -171,7 +175,7 @@ wire [7:0] sid_data = (sid_type[0] & RnW & cs_sid) ? sid6581_data : (sid_type[ // ----------------------------------------------------------------------- -wire [16:0] mix_audio = sid_audio + {ted_audio,ted_audio,ted_audio}; +wire [16:0] mix_audio = sid_audio + {ted_audio,ted_audio,ted_audio} + {cass_aud, 10'd0}; assign sound = ($signed(mix_audio) > $signed(17'd32767)) ? 16'd32767 : ($signed(mix_audio) < $signed(-17'd32768)) ? $signed(-16'd32768) : mix_audio[15:0]; // ----------------------------------------------------------------------- @@ -277,7 +281,7 @@ always @(posedge CLK28) begin end // connect IEC bus -assign port_in[5:0]=0; +assign {port_in[5],port_in[3:0]}=0; assign IEC_DATAOUT=port_out[0]; assign port_in[7]=~(iec_data|port_out[0]); assign IEC_CLKOUT=port_out[1]; @@ -285,4 +289,7 @@ assign port_in[6]=~(iec_clk|port_out[1]); assign IEC_ATNOUT=port_out[2]; assign IEC_RESET=sreset; +assign cass_mtr = port_out[3]; +assign port_in[4]= cass_in; + endmodule diff --git a/ddram.sv b/ddram.sv new file mode 100644 index 0000000..3d346d8 --- /dev/null +++ b/ddram.sv @@ -0,0 +1,124 @@ +// +// ddram.v +// +// DE10-nano DDR3 memory interface +// +// Copyright (c) 2017 Sorgelig +// +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// + +// 8-bit version + +module ddram +( + input reset, + input DDRAM_CLK, + + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + input [27:0] addr, // 256MB at the end of 1GB + output [7:0] dout, // data output to cpu + input [7:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output ready // dout is valid. Ready to accept new read/write. +); + +assign DDRAM_BURSTCNT = 1; +assign DDRAM_BE = (8'd1< -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// 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'reconfig_to_pll' - input wire [63:0] reconfig_to_pll, - - // interface 'reconfig_from_pll' - output wire [63:0] reconfig_from_pll -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .pll_fractional_cout(32), - .pll_dsm_out_sel("1st_order"), - .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("57.272598 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("Cyclone V"), - .pll_subtype("Reconfigurable"), - .m_cnt_hi_div(5), - .m_cnt_lo_div(4), - .n_cnt_hi_div(256), - .n_cnt_lo_div(256), - .m_cnt_bypass_en("false"), - .n_cnt_bypass_en("true"), - .m_cnt_odd_div_duty_en("true"), - .n_cnt_odd_div_duty_en("false"), - .c_cnt_hi_div0(4), - .c_cnt_lo_div0(4), - .c_cnt_prst0(1), - .c_cnt_ph_mux_prst0(0), - .c_cnt_in_src0("ph_mux_clk"), - .c_cnt_bypass_en0("false"), - .c_cnt_odd_div_duty_en0("false"), - .c_cnt_hi_div1(1), - .c_cnt_lo_div1(1), - .c_cnt_prst1(1), - .c_cnt_ph_mux_prst1(0), - .c_cnt_in_src1("ph_mux_clk"), - .c_cnt_bypass_en1("true"), - .c_cnt_odd_div_duty_en1("false"), - .c_cnt_hi_div2(1), - .c_cnt_lo_div2(1), - .c_cnt_prst2(1), - .c_cnt_ph_mux_prst2(0), - .c_cnt_in_src2("ph_mux_clk"), - .c_cnt_bypass_en2("true"), - .c_cnt_odd_div_duty_en2("false"), - .c_cnt_hi_div3(1), - .c_cnt_lo_div3(1), - .c_cnt_prst3(1), - .c_cnt_ph_mux_prst3(0), - .c_cnt_in_src3("ph_mux_clk"), - .c_cnt_bypass_en3("true"), - .c_cnt_odd_div_duty_en3("false"), - .c_cnt_hi_div4(1), - .c_cnt_lo_div4(1), - .c_cnt_prst4(1), - .c_cnt_ph_mux_prst4(0), - .c_cnt_in_src4("ph_mux_clk"), - .c_cnt_bypass_en4("true"), - .c_cnt_odd_div_duty_en4("false"), - .c_cnt_hi_div5(1), - .c_cnt_lo_div5(1), - .c_cnt_prst5(1), - .c_cnt_ph_mux_prst5(0), - .c_cnt_in_src5("ph_mux_clk"), - .c_cnt_bypass_en5("true"), - .c_cnt_odd_div_duty_en5("false"), - .c_cnt_hi_div6(1), - .c_cnt_lo_div6(1), - .c_cnt_prst6(1), - .c_cnt_ph_mux_prst6(0), - .c_cnt_in_src6("ph_mux_clk"), - .c_cnt_bypass_en6("true"), - .c_cnt_odd_div_duty_en6("false"), - .c_cnt_hi_div7(1), - .c_cnt_lo_div7(1), - .c_cnt_prst7(1), - .c_cnt_ph_mux_prst7(0), - .c_cnt_in_src7("ph_mux_clk"), - .c_cnt_bypass_en7("true"), - .c_cnt_odd_div_duty_en7("false"), - .c_cnt_hi_div8(1), - .c_cnt_lo_div8(1), - .c_cnt_prst8(1), - .c_cnt_ph_mux_prst8(0), - .c_cnt_in_src8("ph_mux_clk"), - .c_cnt_bypass_en8("true"), - .c_cnt_odd_div_duty_en8("false"), - .c_cnt_hi_div9(1), - .c_cnt_lo_div9(1), - .c_cnt_prst9(1), - .c_cnt_ph_mux_prst9(0), - .c_cnt_in_src9("ph_mux_clk"), - .c_cnt_bypass_en9("true"), - .c_cnt_odd_div_duty_en9("false"), - .c_cnt_hi_div10(1), - .c_cnt_lo_div10(1), - .c_cnt_prst10(1), - .c_cnt_ph_mux_prst10(0), - .c_cnt_in_src10("ph_mux_clk"), - .c_cnt_bypass_en10("true"), - .c_cnt_odd_div_duty_en10("false"), - .c_cnt_hi_div11(1), - .c_cnt_lo_div11(1), - .c_cnt_prst11(1), - .c_cnt_ph_mux_prst11(0), - .c_cnt_in_src11("ph_mux_clk"), - .c_cnt_bypass_en11("true"), - .c_cnt_odd_div_duty_en11("false"), - .c_cnt_hi_div12(1), - .c_cnt_lo_div12(1), - .c_cnt_prst12(1), - .c_cnt_ph_mux_prst12(0), - .c_cnt_in_src12("ph_mux_clk"), - .c_cnt_bypass_en12("true"), - .c_cnt_odd_div_duty_en12("false"), - .c_cnt_hi_div13(1), - .c_cnt_lo_div13(1), - .c_cnt_prst13(1), - .c_cnt_ph_mux_prst13(0), - .c_cnt_in_src13("ph_mux_clk"), - .c_cnt_bypass_en13("true"), - .c_cnt_odd_div_duty_en13("false"), - .c_cnt_hi_div14(1), - .c_cnt_lo_div14(1), - .c_cnt_prst14(1), - .c_cnt_ph_mux_prst14(0), - .c_cnt_in_src14("ph_mux_clk"), - .c_cnt_bypass_en14("true"), - .c_cnt_odd_div_duty_en14("false"), - .c_cnt_hi_div15(1), - .c_cnt_lo_div15(1), - .c_cnt_prst15(1), - .c_cnt_ph_mux_prst15(0), - .c_cnt_in_src15("ph_mux_clk"), - .c_cnt_bypass_en15("true"), - .c_cnt_odd_div_duty_en15("false"), - .c_cnt_hi_div16(1), - .c_cnt_lo_div16(1), - .c_cnt_prst16(1), - .c_cnt_ph_mux_prst16(0), - .c_cnt_in_src16("ph_mux_clk"), - .c_cnt_bypass_en16("true"), - .c_cnt_odd_div_duty_en16("false"), - .c_cnt_hi_div17(1), - .c_cnt_lo_div17(1), - .c_cnt_prst17(1), - .c_cnt_ph_mux_prst17(0), - .c_cnt_in_src17("ph_mux_clk"), - .c_cnt_bypass_en17("true"), - .c_cnt_odd_div_duty_en17("false"), - .pll_vco_div(2), - .pll_cp_current(20), - .pll_bwctrl(4000), - .pll_output_clk_frequency("458.180784 MHz"), - .pll_fractional_division("702723995"), - .mimic_fbclk_type("none"), - .pll_fbclk_mux_1("glb"), - .pll_fbclk_mux_2("m_cnt"), - .pll_m_cnt_in_src("ph_mux_clk"), - .pll_slf_rst("true") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_0}), - .locked (locked), - .reconfig_to_pll (reconfig_to_pll), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk), - .reconfig_from_pll (reconfig_from_pll) - ); -endmodule - diff --git a/pll2/pll2_0002_q13.qip b/pll2/pll2_0002_q13.qip deleted file mode 100644 index d218ebe..0000000 --- a/pll2/pll2_0002_q13.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll2_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll2_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll2_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll2_0002*|altera_pll:altera_pll_i*|*" diff --git a/pll2_q13.qip b/pll2_q13.qip deleted file mode 100644 index f4c6b5e..0000000 --- a/pll2_q13.qip +++ /dev/null @@ -1,13 +0,0 @@ -set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll2" -name MISC_FILE [file join $::quartus(qip_path) "pll2.cmp"] -set_global_assignment -name SYNTHESIS_ONLY_QIP ON - -set_global_assignment -library "pll2" -name VERILOG_FILE [file join $::quartus(qip_path) "pll2.v"] -set_global_assignment -library "pll2" -name VERILOG_FILE [file join $::quartus(qip_path) "pll2/pll2_0002.v"] -set_global_assignment -library "pll2" -name QIP_FILE [file join $::quartus(qip_path) "pll2/pll2_0002_q13.qip"] - -set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll.qip b/sys/pll.qip index 3722b76..38f56b9 100644 --- a/sys/pll.qip +++ b/sys/pll.qip @@ -31,21 +31,23 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::dHJ1ZQ==::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::OQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MzQzODI4Mjgx::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTM3NDM4OTUzNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTM=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::OA==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzQzODI4Mjgx::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" @@ -256,7 +258,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MzIuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzUwMzM2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" @@ -312,13 +314,157 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NQ==::bV9jbnRfaGlfZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::dHJ1ZQ==::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::NA==::Y19jbnRfaGlfZGl2MA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::NA==::Y19jbnRfbG9fZGl2MA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MzA=::cGxsX2NwX2N1cnJlbnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::MjAwMA==::cGxsX2J3Y3RybA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDU0LjAwMjY4NyBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzQzODI4Mjgx::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw3LDYsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE2LjAgTUh6LDEzNzQzODk1MzUsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDQsNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyLDMwLDIwMDAsNDU0LjAwMjY4NyBNSHosMzQzODI4MjgxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" diff --git a/sys/pll.v b/sys/pll.v index 79f345c..64370dd 100644 --- a/sys/pll.v +++ b/sys/pll.v @@ -2,21 +2,25 @@ // GENERATION: XML // pll.v -// Generated using ACDS version 17.0 598 +// Generated using ACDS version 17.0 602 `timescale 1 ps / 1 ps module pll ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0, // outclk0.clk - output wire locked // locked.export + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire locked, // locked.export + input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll ); pll_0002 pll_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .locked (locked) // locked.export + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .locked (locked), // locked.export + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll ); endmodule @@ -26,7 +30,7 @@ endmodule // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ -// Copyright (C) 1991-2018 Altera Corporation +// Copyright (C) 1991-2019 Altera Corporation // Any megafunction design, and related net list (encrypted or decrypted), // support information, device programming or simulation file, and any other // associated documentation or information provided by Altera or a partner @@ -60,14 +64,14 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: -// Retrieval info: -// Retrieval info: +// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -229,7 +233,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/sys/pll/pll_0002.qip b/sys/pll/pll_0002.qip index 9f8ded1..fc13da8 100644 --- a/sys/pll/pll_0002.qip +++ b/sys/pll/pll_0002.qip @@ -1,4 +1,2 @@ set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v index 8f54447..0489ad2 100644 --- a/sys/pll/pll_0002.v +++ b/sys/pll/pll_0002.v @@ -11,15 +11,23 @@ module pll_0002( output wire outclk_0, // interface 'locked' - output wire locked + output wire locked, + + // interface 'reconfig_to_pll' + input wire [63:0] reconfig_to_pll, + + // interface 'reconfig_from_pll' + output wire [63:0] reconfig_from_pll ); altera_pll #( .fractional_vco_multiplier("true"), .reference_clock_frequency("50.0 MHz"), + .pll_fractional_cout(32), + .pll_dsm_out_sel("1st_order"), .operation_mode("direct"), .number_of_clocks(1), - .output_clock_frequency0("32.000000 MHz"), + .output_clock_frequency0("56.750336 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), .output_clock_frequency1("0 MHz"), @@ -73,15 +81,161 @@ module pll_0002( .output_clock_frequency17("0 MHz"), .phase_shift17("0 ps"), .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") + .pll_type("Cyclone V"), + .pll_subtype("Reconfigurable"), + .m_cnt_hi_div(5), + .m_cnt_lo_div(4), + .n_cnt_hi_div(256), + .n_cnt_lo_div(256), + .m_cnt_bypass_en("false"), + .n_cnt_bypass_en("true"), + .m_cnt_odd_div_duty_en("true"), + .n_cnt_odd_div_duty_en("false"), + .c_cnt_hi_div0(4), + .c_cnt_lo_div0(4), + .c_cnt_prst0(1), + .c_cnt_ph_mux_prst0(0), + .c_cnt_in_src0("ph_mux_clk"), + .c_cnt_bypass_en0("false"), + .c_cnt_odd_div_duty_en0("false"), + .c_cnt_hi_div1(1), + .c_cnt_lo_div1(1), + .c_cnt_prst1(1), + .c_cnt_ph_mux_prst1(0), + .c_cnt_in_src1("ph_mux_clk"), + .c_cnt_bypass_en1("true"), + .c_cnt_odd_div_duty_en1("false"), + .c_cnt_hi_div2(1), + .c_cnt_lo_div2(1), + .c_cnt_prst2(1), + .c_cnt_ph_mux_prst2(0), + .c_cnt_in_src2("ph_mux_clk"), + .c_cnt_bypass_en2("true"), + .c_cnt_odd_div_duty_en2("false"), + .c_cnt_hi_div3(1), + .c_cnt_lo_div3(1), + .c_cnt_prst3(1), + .c_cnt_ph_mux_prst3(0), + .c_cnt_in_src3("ph_mux_clk"), + .c_cnt_bypass_en3("true"), + .c_cnt_odd_div_duty_en3("false"), + .c_cnt_hi_div4(1), + .c_cnt_lo_div4(1), + .c_cnt_prst4(1), + .c_cnt_ph_mux_prst4(0), + .c_cnt_in_src4("ph_mux_clk"), + .c_cnt_bypass_en4("true"), + .c_cnt_odd_div_duty_en4("false"), + .c_cnt_hi_div5(1), + .c_cnt_lo_div5(1), + .c_cnt_prst5(1), + .c_cnt_ph_mux_prst5(0), + .c_cnt_in_src5("ph_mux_clk"), + .c_cnt_bypass_en5("true"), + .c_cnt_odd_div_duty_en5("false"), + .c_cnt_hi_div6(1), + .c_cnt_lo_div6(1), + .c_cnt_prst6(1), + .c_cnt_ph_mux_prst6(0), + .c_cnt_in_src6("ph_mux_clk"), + .c_cnt_bypass_en6("true"), + .c_cnt_odd_div_duty_en6("false"), + .c_cnt_hi_div7(1), + .c_cnt_lo_div7(1), + .c_cnt_prst7(1), + .c_cnt_ph_mux_prst7(0), + .c_cnt_in_src7("ph_mux_clk"), + .c_cnt_bypass_en7("true"), + .c_cnt_odd_div_duty_en7("false"), + .c_cnt_hi_div8(1), + .c_cnt_lo_div8(1), + .c_cnt_prst8(1), + .c_cnt_ph_mux_prst8(0), + .c_cnt_in_src8("ph_mux_clk"), + .c_cnt_bypass_en8("true"), + .c_cnt_odd_div_duty_en8("false"), + .c_cnt_hi_div9(1), + .c_cnt_lo_div9(1), + .c_cnt_prst9(1), + .c_cnt_ph_mux_prst9(0), + .c_cnt_in_src9("ph_mux_clk"), + .c_cnt_bypass_en9("true"), + .c_cnt_odd_div_duty_en9("false"), + .c_cnt_hi_div10(1), + .c_cnt_lo_div10(1), + .c_cnt_prst10(1), + .c_cnt_ph_mux_prst10(0), + .c_cnt_in_src10("ph_mux_clk"), + .c_cnt_bypass_en10("true"), + .c_cnt_odd_div_duty_en10("false"), + .c_cnt_hi_div11(1), + .c_cnt_lo_div11(1), + .c_cnt_prst11(1), + .c_cnt_ph_mux_prst11(0), + .c_cnt_in_src11("ph_mux_clk"), + .c_cnt_bypass_en11("true"), + .c_cnt_odd_div_duty_en11("false"), + .c_cnt_hi_div12(1), + .c_cnt_lo_div12(1), + .c_cnt_prst12(1), + .c_cnt_ph_mux_prst12(0), + .c_cnt_in_src12("ph_mux_clk"), + .c_cnt_bypass_en12("true"), + .c_cnt_odd_div_duty_en12("false"), + .c_cnt_hi_div13(1), + .c_cnt_lo_div13(1), + .c_cnt_prst13(1), + .c_cnt_ph_mux_prst13(0), + .c_cnt_in_src13("ph_mux_clk"), + .c_cnt_bypass_en13("true"), + .c_cnt_odd_div_duty_en13("false"), + .c_cnt_hi_div14(1), + .c_cnt_lo_div14(1), + .c_cnt_prst14(1), + .c_cnt_ph_mux_prst14(0), + .c_cnt_in_src14("ph_mux_clk"), + .c_cnt_bypass_en14("true"), + .c_cnt_odd_div_duty_en14("false"), + .c_cnt_hi_div15(1), + .c_cnt_lo_div15(1), + .c_cnt_prst15(1), + .c_cnt_ph_mux_prst15(0), + .c_cnt_in_src15("ph_mux_clk"), + .c_cnt_bypass_en15("true"), + .c_cnt_odd_div_duty_en15("false"), + .c_cnt_hi_div16(1), + .c_cnt_lo_div16(1), + .c_cnt_prst16(1), + .c_cnt_ph_mux_prst16(0), + .c_cnt_in_src16("ph_mux_clk"), + .c_cnt_bypass_en16("true"), + .c_cnt_odd_div_duty_en16("false"), + .c_cnt_hi_div17(1), + .c_cnt_lo_div17(1), + .c_cnt_prst17(1), + .c_cnt_ph_mux_prst17(0), + .c_cnt_in_src17("ph_mux_clk"), + .c_cnt_bypass_en17("true"), + .c_cnt_odd_div_duty_en17("false"), + .pll_vco_div(2), + .pll_cp_current(30), + .pll_bwctrl(2000), + .pll_output_clk_frequency("454.002687 MHz"), + .pll_fractional_division("343828281"), + .mimic_fbclk_type("none"), + .pll_fbclk_mux_1("glb"), + .pll_fbclk_mux_2("m_cnt"), + .pll_m_cnt_in_src("ph_mux_clk"), + .pll_slf_rst("true") ) altera_pll_i ( .rst (rst), .outclk ({outclk_0}), .locked (locked), + .reconfig_to_pll (reconfig_to_pll), .fboutclk ( ), .fbclk (1'b0), - .refclk (refclk) + .refclk (refclk), + .reconfig_from_pll (reconfig_from_pll) ); endmodule diff --git a/sys/pll/pll_0002_q13.qip b/sys/pll/pll_0002_q13.qip new file mode 100644 index 0000000..9f8ded1 --- /dev/null +++ b/sys/pll/pll_0002_q13.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip new file mode 100644 index 0000000..a5cd7dc --- /dev/null +++ b/sys/pll_q13.qip @@ -0,0 +1,13 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON + +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] +set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/sys/sys_q13.qip b/sys/sys_q13.qip index 760991a..a5c5255 100644 --- a/sys/sys_q13.qip +++ b/sys/sys_q13.qip @@ -1,8 +1,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ] set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_q13.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ] diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 4cb8b0b..39a627c 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -15,8 +15,7 @@ derive_clock_uncertainty # Decouple different clock groups (to simplify routing) set_clock_groups -asynchronous \ - -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -group [get_clocks { *|pll2|pll2_inst|altera_pll_i|cyclonev_pll|counter[*].output_counter|divclk}] \ + -group [get_clocks { *|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[*].output_counter|divclk}] \ -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -group [get_clocks { *|h2f_user0_clk}] \ -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] diff --git a/tap_fifo.vhd b/tap_fifo.vhd new file mode 100644 index 0000000..4ea7fe1 --- /dev/null +++ b/tap_fifo.vhd @@ -0,0 +1,190 @@ +-- megafunction wizard: %FIFO% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: scfifo + +-- ============================================================ +-- File Name: tap_fifo.vhd +-- Megafunction Name(s): +-- scfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY tap_fifo IS + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END tap_fifo; + + +ARCHITECTURE SYN OF tap_fifo IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + empty <= sub_wire0; + full <= sub_wire1; + q <= sub_wire2(7 DOWNTO 0); + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone III", + lpm_numwords => 64, + lpm_showahead => "OFF", + lpm_type => "scfifo", + lpm_width => 8, + lpm_widthu => 6, + overflow_checking => "ON", + underflow_checking => "ON", + use_eab => "ON" + ) + PORT MAP ( + aclr => aclr, + clock => clock, + data => data, + rdreq => rdreq, + wrreq => wrreq, + empty => sub_wire0, + full => sub_wire1, + q => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "64" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "0" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf