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131 lines
4.5 KiB
Verilog
131 lines
4.5 KiB
Verilog
//**************************************************************************
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// hp_bytequad.v - wrapper for 4 FIFOs in the host to parasite direction.
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//
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// COPYRIGHT 2010 Richard Evans, Ed Spittles
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//
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// This file is part of tube - an Acorn Tube ULA compatible system.
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//
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// tube is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// tube is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with tube. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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`timescale 1ns / 1ns
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module hp_bytequad (
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input h_rst_b,
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input h_we_b,
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input [3:0] h_selectData,
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input h_phi2,
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input [7:0] h_data,
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input [3:0] p_selectData,
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input p_phi2,
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input p_rdnw,
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input one_byte_mode,
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output [7:0] p_data,
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output [3:0] p_data_available,
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output p_r3_two_bytes_available,
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output [3:0] h_full
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);
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// Declare registers and wires
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reg [7:0] p_datamux_r;
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wire [3:0] h_full_pre_w;
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wire [7:0] fifo0_w,
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fifo1_w,
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fifo2_w,
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fifo3_w;
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// assign primary IOs
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assign p_data = p_datamux_r;
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assign h_full = h_full_pre_w;
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// Combinatorial code for the data output
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always @ (fifo0_w or
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fifo1_w or
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fifo2_w or
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fifo3_w or
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p_selectData
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)
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casex (p_selectData)
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4'bxxx1: p_datamux_r = fifo0_w;
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4'bxx10: p_datamux_r = fifo1_w;
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4'bx100: p_datamux_r = fifo2_w;
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4'b1000: p_datamux_r = fifo3_w;
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default: p_datamux_r = 8'bx;
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endcase // case p_selectData
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// module instances
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hp_byte reg1 (
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.h_rst_b(h_rst_b),
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.h_we_b(h_we_b),
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.h_selectData(h_selectData[0]),
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.h_phi2(h_phi2),
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.h_data(h_data),
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.p_selectData(p_selectData[0]),
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.p_phi2(p_phi2),
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.p_rdnw(p_rdnw),
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.p_data(fifo0_w),
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.p_data_available(p_data_available[0]),
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.h_full(h_full_pre_w[0])
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);
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hp_byte reg2 (
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.h_rst_b(h_rst_b),
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.h_we_b(h_we_b),
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.h_selectData(h_selectData[1]),
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.h_phi2(h_phi2),
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.h_data(h_data),
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.p_selectData(p_selectData[1]),
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.p_phi2(p_phi2),
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.p_rdnw(p_rdnw),
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.p_data(fifo1_w),
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.p_data_available(p_data_available[1]),
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.h_full(h_full_pre_w[1])
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);
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hp_reg3 reg3 (
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.h_rst_b(h_rst_b),
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.h_we_b(h_we_b),
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.h_selectData( h_selectData[2]),
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.h_phi2(h_phi2),
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.h_data( h_data ),
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.p_selectData( p_selectData[2]),
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.p_phi2(p_phi2),
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.p_rdnw(p_rdnw),
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.one_byte_mode(one_byte_mode),
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.p_data(fifo2_w),
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.p_data_available(p_data_available[2]),
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.p_two_bytes_available( p_r3_two_bytes_available),
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.h_full(h_full_pre_w[2])
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);
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hp_byte reg4 (
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.h_rst_b(h_rst_b),
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.h_we_b(h_we_b),
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.h_selectData(h_selectData[3]),
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.h_phi2(h_phi2),
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.h_data(h_data),
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.p_selectData(p_selectData[3]),
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.p_phi2(p_phi2),
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.p_rdnw(p_rdnw),
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.p_data(fifo3_w),
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.p_data_available(p_data_available[3]),
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.h_full(h_full_pre_w[3])
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);
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endmodule // hp_byte
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