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73 lines
2.5 KiB
Verilog
73 lines
2.5 KiB
Verilog
//**************************************************************************
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// hp_byte.v - single byte buffer for transfers in host to parasite direction
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//
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// COPYRIGHT 2010 Richard Evans, Ed Spittles
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//
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// This file is part of tube - an Acorn Tube ULA compatible system.
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//
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// tube is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// tube is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with tube. If not, see <http://www.gnu.org/licenses/>.
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//
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// **************************************************************************
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`timescale 1ns / 1ns
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module hp_byte (
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input h_rst_b,
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input h_we_b,
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input h_selectData,
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input h_phi2,
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input [7:0] h_data,
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input p_selectData,
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input p_phi2,
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input p_rdnw,
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output [7:0] p_data,
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output p_data_available,
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output h_full
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);
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reg [7:0] fifo_q_r ;
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wire [7:0] fifo_d_w ;
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// assign primary IOs
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assign p_data = fifo_q_r;
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// Compute D and resets for state bits
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assign fifo_d_w = ( h_selectData & !h_we_b ) ? h_data : fifo_q_r;
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// Instance the appropriate flag logic
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hp_flag_m flag_0 (
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.rst_b(h_rst_b),
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.p1_rdnw( h_we_b),
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.p1_select(h_selectData),
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.p1_clk(h_phi2),
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.p2_select(p_selectData),
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.p2_rdnw(p_rdnw),
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.p2_clk(p_phi2 ),
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.p2_data_available(p_data_available),
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.p1_full(h_full)
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);
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// All state inferences
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always @ ( negedge h_phi2 or negedge h_rst_b )
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begin
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if ( ! h_rst_b)
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fifo_q_r <= 8'b0;
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else
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fifo_q_r <= fifo_d_w ;
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end
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endmodule // hp_byte
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