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108 lines
2.6 KiB
Verilog
108 lines
2.6 KiB
Verilog
//
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// hps_ext for Atari ST
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//
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// Copyright (c) 2020 Alexey Melnikov
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module hps_ext
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(
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input clk_sys,
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inout [35:0] EXT_BUS,
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output reg dio_in_strobe,
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output reg [15:0] dio_in,
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output reg dio_out_strobe,
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input [15:0] dio_out,
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output reg dma_ack,
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output reg [7:0] dma_status,
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output reg dma_nak,
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input [7:0] dio_status,
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output [3:0] dio_status_idx
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);
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assign EXT_BUS[15:0] = io_dout;
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wire [15:0] io_din = EXT_BUS[31:16];
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assign EXT_BUS[32] = dout_en;
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wire io_strobe = EXT_BUS[33];
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wire io_enable = EXT_BUS[34];
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localparam EXT_CMD_MIN = ST_WRITE_MEMORY;
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localparam EXT_CMD_MAX = ST_GET_DMASTATE;
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localparam ST_WRITE_MEMORY = 8;
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localparam ST_READ_MEMORY = 9;
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localparam ST_ACK_DMA = 10;
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localparam ST_NAK_DMA = 11;
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localparam ST_GET_DMASTATE = 12;
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reg [15:0] io_dout;
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reg dout_en = 0;
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reg [9:0] byte_cnt;
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assign dio_status_idx = byte_cnt[3:0] - 1'd1;
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always@(posedge clk_sys) begin
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reg [15:0] cmd;
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if(~io_enable) begin
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dout_en <= 0;
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io_dout <= 0;
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byte_cnt <= 0;
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end
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else if(io_strobe) begin
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io_dout <= 0;
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if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
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if(byte_cnt == 0) begin
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cmd <= io_din;
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dout_en <= (io_din >= EXT_CMD_MIN && io_din <= EXT_CMD_MAX);
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if(io_din == ST_NAK_DMA) dma_nak <= ~dma_nak;
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end else begin
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case(cmd)
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ST_WRITE_MEMORY:
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begin
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dio_in <= {io_din[7:0], io_din[15:8]};
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dio_in_strobe <= ~dio_in_strobe;
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end
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ST_READ_MEMORY:
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begin
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io_dout <= {dio_out[7:0], dio_out[15:8]};
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dio_out_strobe <= ~dio_out_strobe;
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end
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ST_ACK_DMA:
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begin
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dma_ack <= ~dma_ack;
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dma_status <= io_din[7:0];
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end
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ST_GET_DMASTATE:
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begin
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io_dout <= dio_status;
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end
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endcase
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end
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end
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end
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endmodule
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