From d69efedcd92e85772fefbdeb19e35682bc6bb539 Mon Sep 17 00:00:00 2001 From: Wojciech Mostowski Date: Sun, 30 Mar 2025 15:16:07 +0200 Subject: [PATCH] Somewhat nicer PBI BIOS splash --- firmware/PBIBIOS.mif | 16 +++++----- firmware/pbi_bios.asm | 58 ++++++++++++++++++++-------------- rtl/common/a8core/pbi_rom.vhdl | 9 ++---- 3 files changed, 46 insertions(+), 37 deletions(-) diff --git a/firmware/PBIBIOS.mif b/firmware/PBIBIOS.mif index c286e79..ad6caec 100644 --- a/firmware/PBIBIOS.mif +++ b/firmware/PBIBIOS.mif @@ -7,15 +7,15 @@ WIDTH = 8; ADDRESS_RADIX = HEX; DATA_RADIX = HEX; CONTENT BEGIN -0000: 4D 53 54 80 31 4C 42 D8 60 EA EA 91 00 08 D8 08 D8 08 D8 08 D8 08 D8 08; +0000: 4D 53 54 80 31 4C BF D8 60 EA EA 91 00 08 D8 08 D8 08 D8 08 D8 08 D8 08; 0018: D8 AD 47 02 0D 48 02 8D 47 02 A9 00 A2 FE 9D FF D0 CA D0 FA A9 A5 8D 00; -0030: D1 8D 01 D1 A0 00 A2 00 8E 1A D0 E8 D0 FA C8 D0 F5 60 AD 00 03 C9 31 D0; -0048: 0E AD 01 03 F0 09 C9 05 B0 05 20 00 DC 38 60 18 60 FF FF FF FF FF FF FF; -0060: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -0078: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -0090: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -00A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -00C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0030: D1 8D 01 D1 A9 0C 8D C5 02 A9 E0 8D 09 D4 A9 5E 8D 02 D4 A9 D8 8D 03 D4; +0048: A5 14 C5 14 F0 FC A0 22 8C 00 D4 18 69 78 C5 14 D0 FC 8E 00 D4 60 70 70; +0060: 70 42 6F D8 10 42 97 D8 70 42 10 D1 41 5E D8 00 00 21 74 61 72 69 18 10; +0078: 10 00 2D 69 33 34 65 72 00 63 6F 72 65 00 30 22 29 00 22 29 2F 33 00 76; +0090: 10 0E 18 00 00 00 00 00 00 08 23 09 00 12 10 12 15 00 77 6F 6A 20 21 74; +00A8: 61 72 69 21 67 65 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 AD; +00C0: 00 03 C9 31 D0 0E AD 01 03 F0 09 C9 05 B0 05 20 00 DC 38 60 18 60 FF FF; 00D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; 00F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; 0108: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; diff --git a/firmware/pbi_bios.asm b/firmware/pbi_bios.asm index a3f29cf..f3ed513 100644 --- a/firmware/pbi_bios.asm +++ b/firmware/pbi_bios.asm @@ -1,14 +1,6 @@ ; Links: ; http://atariki.krap.pl/index.php/ROM_PBI -; RAM area D600-D7FF, 512 bytes, in the bios initialize to some id tag (A5A5??) and zero out the rest -; ROM area D800-DFFF, 2048 bytes, but this can be bank switched -; Locate all this in SDRAM in between Basic (8K) and the OS ROM (16K), this gives 8K in total. -; Further RAM cells should be used by the HSIO handler -; Alternativelly, implement RAM directly as D1xx r/w registers, only a few are needed. -; This would allow to use one more PBI rom bank, internal core RAM routing would not -; be needed, and it could stay active all the time, not only when PBI rom is banked in. - ; [one (?) location in this RAM is a marker for PBI request to the firmware, like with the XEX loader ; one location is for the status code, one for whether we service this at all] ; condition for servicing: @@ -49,16 +41,14 @@ bios1_start .byte 'M', 'S', 'T' ; Magic 1 .byte $80 - .byte $31 + .byte $31 ; ddevic we are servicing pdior_vec - jmp pdior + jmp pdior pdint_vec - rts - nop - nop + rts : nop : nop ; Magic 2 .byte $91 - .byte $00 + .byte $00 ; no CIO .word pdint_vec .word pdint_vec .word pdint_vec @@ -68,19 +58,41 @@ pdint_vec pdinit lda pdvmsk : ora pdvrs : sta pdvmsk - lda #0 - ldx #$fe - sta $d100-1,x : dex : bne *-4 + lda #0 : ldx #$fe : sta $d100-1,x : dex : bne *-4 ; Marker for the core firmware lda #$a5 : sta $d100 : sta $d101 - ; Silly rainbow effect, to be removed / replaced later - ldy #0 -color_loop - ldx #0 - stx colbak : inx : bne *-4 - iny : bne color_loop + ; ask for init + lda #$0c : sta $2c5 ; color 1 + lda #$e0 : sta $d409 ; chbase + lda #display_list : sta $d403 ; display list + lda $14 : cmp $14 : beq *-2 : ldy #$22 : sty $d400 ; dmactl + clc : adc #120 : cmp $14 : bne *-2 : stx $d400 +pdinit_ret rts +display_list + .byte $70, $70, $70 + .byte $42 : .word display_text1 + .byte $10 + .byte $42 : .word display_text2 + .byte $70 + .byte $42 : .word display_text3 + .byte $41 : .word display_list + +display_text1 + .byte 0,0 + .byte 'A'-$20,'tari','8'-$20,'0'-$20,'0'-$20,0,'M'-$20,'i','S'-$20,'T'-$20,'er',0,'core',0 + .byte 'P'-$20,'B'-$20,'I'-$20,0,'B'-$20,'I'-$20,'O'-$20,'S'-$20,0 + .byte 'v','0'-$20,'.'-$20,'8'-$20 +display_text1_len = *-display_text1 + .dsb 40-display_text1_len,0 +display_text2 + .byte 0,0 + .byte '('-$20,'C'-$20,')'-$20,0,'2'-$20,'0'-$20,'2'-$20,'5'-$20,0,'woj','@'-$20,'A'-$20,'tari','A'-$20,'ge' +display_text2_len = *-display_text2 + .dsb 40-display_text2_len,0 +display_text3 = $d110 + ; The main block I/O routine pdior lda ddevic : cmp #$31 : bne pdior_bail diff --git a/rtl/common/a8core/pbi_rom.vhdl b/rtl/common/a8core/pbi_rom.vhdl index 351c3a2..ddc9c9c 100644 --- a/rtl/common/a8core/pbi_rom.vhdl +++ b/rtl/common/a8core/pbi_rom.vhdl @@ -53,6 +53,9 @@ signal pbi_ram: small_ram; begin +pbi_rom_address <= pbi_rom_bank & a(10 downto 0); +pbi_rom_address_enable <= d8xx and rw and pbi_rom_enable; + process(a, rw, d1xx, pbi_rom_enable, pbi_ram) begin data_out_enable <= '0'; @@ -111,10 +114,4 @@ begin end if; end process; -process(a, rw, d8xx, pbi_rom_enable, pbi_rom_bank) -begin - pbi_rom_address <= pbi_rom_bank & a(10 downto 0); - pbi_rom_address_enable <= d8xx and rw and pbi_rom_enable; -end process; - end vhdl;