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136 lines
3.2 KiB
Verilog
136 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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/* vidc_fifo.v
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Copyright (c) 2012-2014, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module vidc_fifo #(
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parameter FIFO_SIZE = 3
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)
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(
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input rst,
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input wr_clk,
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input wr_en,
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input[31:0] din,
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input rd_clk,
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input rd_ce,
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input rd_en,
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output reg [7:0] dout,
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output reg [WORD_WIDTH-1:0] wr_ptr,
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output reg [WORD_WIDTH-1:0] space,
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output reg full,
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output empty
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);
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localparam MEM_DEPTH = 2**FIFO_SIZE;
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localparam WORD_WIDTH = FIFO_SIZE;
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localparam BYTE_WIDTH = FIFO_SIZE + 2;
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reg [31:0] data[0:MEM_DEPTH-1];
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reg [BYTE_WIDTH-1:0] rd_ptr;
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integer k;
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initial begin
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wr_ptr = 'd0;
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rd_ptr = 'd0;
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full = 1'b0;
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dout = 8'd0;
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for (k = 0; k < MEM_DEPTH; k = k + 1)
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begin
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data[k] = 32'd0;
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end
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$display("FIFO has %x", MEM_DEPTH);
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end
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reg [BYTE_WIDTH-1:0] rd_ptr_r;
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always @(posedge wr_clk) begin
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reg rstD, rstD2;
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rd_ptr_r <= rd_ptr;
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space <= {rd_ptr_r[BYTE_WIDTH-1:2]} - wr_ptr;
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rstD <= rst;
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rstD2 <= rstD;
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if (rstD2) begin
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wr_ptr <= 'd0;
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full <= 1'b0;
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end else begin
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if (wr_ptr != {rd_ptr_r[BYTE_WIDTH-1:2]}) begin
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full <= 1'b0;
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end
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if (wr_en == 1'b1) begin
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data[wr_ptr] <= din;
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wr_ptr <= wr_ptr + 2'd1;
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full <= (wr_ptr + 2'd1) == {rd_ptr_r[BYTE_WIDTH-1:2]};
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end
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end
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end
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wire [7:0] q;
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always @(posedge rd_clk) begin
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reg rstD, rstD2;
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rstD <= rst;
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rstD2 <= rstD;
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if(rd_ce) begin
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if (rstD2) begin
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rd_ptr <= 'd0;
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dout <= 8'd0;
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end else if (rd_en) begin
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if (~empty) begin
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rd_ptr <= rd_ptr + 1'd1;
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dout <= q;
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end else begin
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dout <= 'd0;
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end
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end
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end
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end
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assign empty = !full & space == 'd0;
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// cross the clock domain.
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assign q = data[{rd_ptr[BYTE_WIDTH-1:2]}][{rd_ptr[1:0],3'b000} +:8];
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endmodule
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