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62 lines
1.7 KiB
Verilog
62 lines
1.7 KiB
Verilog
`timescale 1 ps / 1 ps
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module sram_byte_en
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#(
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parameter DATA_WIDTH = 128,
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parameter ADDRESS_WIDTH = 7
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)
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(
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input i_clk,
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input [DATA_WIDTH-1:0] i_write_data,
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input i_write_enable,
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input [ADDRESS_WIDTH-1:0] i_address,
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input [DATA_WIDTH/8-1:0] i_byte_enable,
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output [DATA_WIDTH-1:0] o_read_data
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);
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wire [DATA_WIDTH-1:0] sub_wire0;
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assign o_read_data = sub_wire0;
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altsyncram altsyncram_component (
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.address_a (i_address),
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.byteena_a (i_byte_enable),
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.clock0 (i_clk),
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.data_a (i_write_data),
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.wren_a (i_write_enable),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.byte_size = 8,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 2**ADDRESS_WIDTH,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = ADDRESS_WIDTH,
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altsyncram_component.width_a = DATA_WIDTH,
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altsyncram_component.width_byteena_a = DATA_WIDTH/8;
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endmodule |