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81 lines
2.9 KiB
Verilog
81 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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/* podules.v
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Copyright (c) 2015, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module podules(
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input clkcpu, // system cpu clock.
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input clk8m_en, // goes high in sync with 32m clock to give simulated 8mhz
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input clk2m_en, // goes high in sync with 32m clock to give simulated 2mhz
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input rst_i, // reset
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input [1:0] speed_i, // podule access speed. (redundant except for address decode).
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// "wishbone bus" the ack is externally generated currently.
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [15:2] wb_adr, // la
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input [15:0] wb_dat_i, // bd
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output[15:0] wb_dat_o // bd
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// place any signals that need to be passed up to the top after here.
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);
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localparam PODULE0 = 2'b00;
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localparam PODULE1 = 2'b01;
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localparam PODULE2 = 2'b10;
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localparam PODULE3 = 2'b11;
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wire [1:0] podule_addr = wb_adr[15:14];
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wire [3:0] podule_select = podule_addr == PODULE0 ? 4'b0001 :
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podule_addr == PODULE1 ? 4'b0010 :
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podule_addr == PODULE2 ? 4'b0100 :
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podule_addr == PODULE3 ? 4'b1000 : 4'd0;
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wire [15:0] pod0_dat;
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wire [15:0] pod1_dat;
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wire [15:0] pod2_dat;
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wire [15:0] pod3_dat;
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always @(posedge clkcpu) begin
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end
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// emulate a simple podule as a test for *PODULES
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assign pod0_dat = wb_adr[13:2] == 12'd0 ? {8'd0, 8'b0_1010_000} : 16'hFFFF;
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assign wb_dat_o = podule_select[PODULE0] ? pod0_dat : 16'hFFFF;
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endmodule
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